E0C88832/88862 TECHNICAL MANUAL
EPSON
87
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer)
PRUN0, PRUN1: 00FF31H•D0, 00FF32H•D0
Controls the RUN/STOP of the counter.
When "1" is written: RUN
When "0" is written: STOP
Reading:
Valid
The counter of timer 0 starts down-counting by
writing "1" to PRUN0 and stops by writing "0".
In the STOP status, the counter data is maintained
until it is preset or set in the next RUN status. Also,
when the STOP status changes to the RUN status,
the data that was maintained can be used for
resuming the count.
In the same way, the RUN/STOP of the timer 1
counter is controlled by PRUN1.
When the 16-bit mode is selected, PRUN1 is fixed at
"0".
At initial reset and when an underflow is generated
in the one-shot mode, this register is set to "0"
(STOP).
CHSEL: 00FF30H•D3
Selects a channel for generating the TOUT signal.
When "1" is written: Timer 0 underflow
When "0" is written: Timer 1 underflow
Reading:
Valid
Select whether the timer 0 underflow will be used
for the TOUT signal or the timer 1 underflow will
be used. When "0" is written to CHSEL, timer 0 is
selected and when "1" is written, timer 1 is
selected.When the 16-bit mode has been selected, it
is fixed to timer 1 (underflow of the 16-bit timer),
and setting of CHSEL becomes invalid.
At initial reset, CHSEL is set to "0" (timer 1
underflow).
PTOUT: 00FF30H•D2
Controls the TOUT (programmable timer output
clock) signal output.
When "1" is written: TOUT signal output ON
When "0" is written: TOUT signal output OFF
Reading:
Valid
PTOUT is the output control register for TOUT
(TOUT) signal. When "1" is set to the register, the
TOUT signal is output from the output port
terminal R27 (R26). When "0" is set, the R27 goes
HIGH (V
DD
) and the R26 goes LOW (V
SS
).
To output the TOUT signal, "1" must always be set
for the data register R27D. The data register R26D
does not affect the TOUT output.
At initial reset, PTOUT is set to "0" (DC output).
The TOUT signal can be output from R26 only
when the function is selected by mask option.
PPT0, PPT1: 00FF21H•D2, D3
Sets the priority level of the programmable timer
interrupt.
The two bits PPT0 and PPT1 are the interrupt
priority register corresponding to the programma-
ble timer interrupt. Table 5.10.10.3 shows the
interrupt priority level which can be set by this
register.
Table 5.10.10.3 Interrupt priority level settings
PPT1
PPT0
Interrupt priority level
1
1
0
0
1
0
1
0
Level 3 (IRQ3)
Level 2 (IRQ2)
Level 1 (IRQ1)
Level 0 (None)
At initial reset, this register is set to "0" (level 0).
EPT0, EPT1: 00FF23H•D6, D7
Enables or disables the generation of an interrupt
for the CPU.
When "1" is written: Interrupt enabled
When "0" is written: Interrupt disabled
Reading:
Valid
The EPT0 and EPT1 are interrupt enable registers
that respectively correspond to the interrupt factors
for timer 0 and timer 1. Interrupts set to "1" are
enabled and interrupts set to "0" are disabled.
When the 16-bit mode is selected, setting of EPT0
becomes invalid.
At initial reset, this register is set to "0" (interrupt
disabled).
FPT0, FPT1: 00FF25H•D6, D7
Indicates the programmable timer interrupt
generation status.
When "1" is read:
Interrupt factor present
When "0" is read:
Interrupt factor not present
When "1" is written: Resets factor flag
When "0" is written: Invalid
The FPT0 and FPT1 are interrupt factor flags that
respectively correspond to the interrupts for timer 0
and timer 1 and are set to "1" in synchronization
with the underflow of each counter.
When set in this manner, if the corresponding
interrupt enable register is set to "1" and the
corresponding interrupt priority register is set to a
higher level than the setting of interrupt flags (I0
and I1), an interrupt will be generated to the CPU.
Regardless of the interrupt enable register and
interrupt priority register settings, the interrupt
factor flag will be set to "1" by the occurrence of an
interrupt generation condition.
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