Pin Name
Module Connector Pin
Connection
Description
VMON_1V0
A-102
VCC_INT
FPGA core voltage
VMON_1V2
B-167
VCC_1V2
1.2 V on-board voltage (de-
fault)/FPGA battery voltage
(assembly option)
VMON_AUX_IO
B-168
VCC_2V0 on-board voltage
(2.0 V for FFG packages, 1.8
V for FBG packages)
VCCAUX_IO
voltage
(required
only
for
FFG
packages)
VMON_DDR3
B-8
VCC_DDR3
DDR3 voltage
Table 16: Voltage Monitoring Outputs
2.12
Clock Generation
A 100 MHz single-ended oscillator and a 200 MHz LVDS oscillator are equipped on the KX2 FPGA
module. The reference clock inputs for the MGT transceivers are available on the module connector pins.
Signal Name
Frequency
FPGA Pin
FPGA Pin Type
Remark
CLK100
100 MHz
AA4
IO_L13P_T2_MRCC_34
Main clock
CLK200_P
200 MHz
AB11
IO_L13P_T2_MRCC_33
LVDS clock
CLK200_N
AC11
IO_L13N_T2_MRCC_33
FPGA_MDIO_EMCCLK
100 MHz
B26
IO_L3N_T0_DQS_EMCCLK_14
External configura-
tion clock
Table 17: Module Clock Resources
2.13
Reset
The FPGA configuration clear signal (FPGA_PROG#) and the FPGA delay configuration signal (FPGA_INIT#)
of the Kintex-7 device are available on the module connector.
Pulling FPGA_PROG# low clears the FPGA configuration. Please refer to the Enclustra Module Pin Connec-
tion Guidelines [10] for general rules regarding the connection of reset pins and to the Xilinx documentation
for details on the functions of the PROGRAM_B_0 and INIT_B_0 signals.
Table 18 presents the available reset signals. Both signals, FPGA_PROG# and FPGA_INIT#, have 10 k
Ω
pull-up
resistors to VCC_CFG_B14 (the pull-ups are built-in in the FTDI status level shifters).
Signal Name
Connector Pin
FPGA Pin Type
Description
FPGA_PROG#
A-132
PROGRAM_B_0
Configuration clear signal
FPGA_INIT#
A-124
INIT_B_0
Delay configuration signal
Table 18: Reset Resources
D-0000-430-002
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Version 06, 25.07.2019
