Figure 10: Power-Up Sequence - VCC_IO in Relation with PWR_GOOD and PWR_EN Signals
2.9.6
Signal Terminations
Differential Inputs
There are no external differential termination resistors on the KX2 FPGA module for differential
inputs. Differential input pairs on the module connector may be terminated either by external termination
resistors on the base board (close to the module pins), or by the FPGA device’s internal termination resistors.
Internal differential termination is available only for certain VCCO voltages; please refer to Xilinx AR# 43989
for details.
Single-Ended Outputs
There are no series termination resistors on the KX2 FPGA module for single-ended outputs. If
required, series termination resistors may be equipped on the base board (close to the module pins).
2.9.7
Analog Inputs
The Kintex-7 FPGA devices provide a dual 12-bit ADC. The auxiliary analog inputs of the FPGA device are
connected to the module connector; these I/Os have the abbreviation “AD” followed by the ADC channel in
the signal name.
The two dedicated ADC pins VP and VN are available on the module connector on pins A-110 and A-112
(FPGA_V_P/N). The ADC can also be used for internal voltage and temperature monitoring. For detailed
information, refer to the Xilinx 7 Series XADC User Guide [16].
The ADC lines are always used differentially; for single-ended applications, the *_N line must be connected
to GND.
Table 9 presents the ADC Parameters.
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Version 06, 25.07.2019
