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3.6.1

Signal Description

Signal Name

Description

FLASH_CLK_FPGA_CCLK

Must be high impedance during configuration and operation

FLASH_DO_FPGA_DIN

Must be high impedance during configuration and operation

FPGA_INIT#

Is pulled low by the FPGA if any CRC error occurs during the configuration; it
may be used as an input to delay the start of the FPGA configuration.

FPGA_DONE

Goes high after a successful FPGA configuration

FPGA_PROG#

When pulled low, the FPGA configuration sequence is cleared and all pins are
tri-stated. The rising edge of FPGA_PROG# initializes the configuration.

FPGA_MODE

Must be pulled low during configuration

FLASH_DI

Must be high impedance during configuration and operation

FLASH_CS#

Must be high impedance during configuration and operation

Table 31: Master Serial Configuration - Signals Description

3.7

Slave Serial Configuration

In the slave serial configuration mode, the bitstream must be transmitted from an external device to the
FPGA. The configuration pins of the FPGA are connected directly to the module connector, allowing the
configuration of the FPGA from a microcontroller or another SPI capable device. For more information on
the configuration modes, please refer to the 7 Series FPGAs Configuration User Guide [17].

For slave serial configuration the bitstream generation option “SPI_buswidth” must be set to 1 in the Xilinx
tools.

3.7.1

Signal Description

Signal Name

Description

FLASH_CLK_FPGA_CCLK

Configuration clock

FLASH_DO_FPGA_DIN

Configuration data

FPGA_INIT#

Is pulled low by the FPGA if any CRC error occurs during the configuration; it
may be used as an input to delay the start of the FPGA configuration.

FPGA_DONE

Goes high after a successful FPGA configuration

FPGA_PROG#

When pulled low, the FPGA configuration sequence is cleared and all pins are
tri-stated. The rising edge of FPGA_PROG# initializes the configuration.

FPGA_MODE

Must be pulled high or left open during configuration

Table 32: Slave Serial Configuration - Signals Description

D-0000-430-002

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Version 06, 25.07.2019

Содержание ME-KX2-160-1C-D10

Страница 1: ...ed description of its features and configuration options In addition references to other useful documents are included Product Information Code Name Product ME KX2 Mercury KX2 FPGA Module Document Inf...

Страница 2: ...s document is strictly confidential and may only be published by Enclustra GmbH Switzerland All referenced trademarks are the property of their respective owners Document History Version Date Author C...

Страница 3: ...wings 12 2 5 1 Top Assembly Drawing 12 2 5 2 Bottom Assembly Drawing 12 2 6 Module Footprint 13 2 7 Mechanical Data 14 2 8 Module Connector 14 2 9 User I O 15 2 9 1 Pinout 15 2 9 2 Differential I Os 1...

Страница 4: ...x JTAG Adapter 34 3 6 Master Serial Configuration 34 3 6 1 Signal Description 35 3 7 Slave Serial Configuration 35 3 7 1 Signal Description 35 3 8 QSPI Flash Programming via JTAG 36 3 9 QSPI Flash Pro...

Страница 5: ...WEEE The Mercury KX2 FPGA module must be properly disposed of at the end of its life The Waste Electrical and Electronic Equipment WEEE Directive 2002 96 EC is not applicable for the Mer cury KX2 FPG...

Страница 6: ...module Mercury KX2 FPGA module documentation available via download Mercury KX2 FPGA Module User Manual this document Mercury KX2 FPGA Module Reference Design 2 Mercury KX2 FPGA Module IO Net Length...

Страница 7: ...MC LPC connector PE1 200 1 FMC HPC connector PE1 300 2 FMC LPC connector PE1 400 2 40 pin Anios pin header 3 12 pin Pmod pin header 5 to 15 V DC supply voltage USB bus power with restrictions Please n...

Страница 8: ...g in the on board QSPI flash via FTDI USB 2 0 controller fitted on the module via an external microcontroller or via the JTAG interface connected to Mer cury module connector The memory subsystem is b...

Страница 9: ...M Controller Range ME KX2 160 1C D10 XC7K160T 1FBG676C 1 GB X 0 to 70 C ME KX2 160 2I D11 P XC7K160T 2FFG676I 2 GB X 40 to 85 C ME KX2 325 2I D11 P XC7K325T 2FFG676I 2 GB X 40 to 85 C ME KX2 410 2I D1...

Страница 10: ...known issues are described in the Mercury KX2 FPGA Module Known Issues and Changes document 6 Article Number Article Code EN101582 ME KX2 160 1C D10 R1 EN101547 ME KX2 160 2I D11 P R1 EN101574 ME KX2...

Страница 11: ...4 Module Top View 2 4 2 Bottom View Figure 5 Module Bottom View Please note that depending on the hardware revision and configuration the module may look slightly dif ferent than shown in this docume...

Страница 12: ...ule Top Assembly Drawing 2 5 2 Bottom Assembly Drawing Figure 7 Module Bottom Assembly Drawing Please note that depending on the hardware revision and configuration the module may look slightly dif fe...

Страница 13: ...e for different PCB design tools Altium PADS Eagle Orcad 7 and include the required information on the module sizes and holes The maximum component height on the base board under the module is depende...

Страница 14: ...Master Pinout Excel Sheet 11 The connector is available in different packaging options and different stacking heights Some examples are presented in Table 5 Please refer to the connector datasheet for...

Страница 15: ...PGA module it may be possible that the connected pins do not have the targeted functions such as primary clocks differential pins MGT signals etc The naming convention for the user I Os is IO_B BANK _...

Страница 16: ...FPGA Module IO Net Length Excel Sheet 3 This enables the user to match the total length of the differential pairs on the base board if required by the application 2 9 3 I O Banks Table 7 describes the...

Страница 17: ...user I O pins The VREF pins are listed in the Mercury Master Pinout Excel Sheet 11 Warning Use only VREF voltages compliant with the equipped FPGA device any other voltages may damage the equipped FPG...

Страница 18: ...tors the VCC_IO_B13 pin that powers I O bank 13 is connected to the on board generated 1 8 V supply voltage Warning Use only VCC_IO voltages compliant with the equipped FPGA device any other voltages...

Страница 19: ...Mercury KX2 FPGA module for single ended outputs If required series termination resistors may be equipped on the base board close to the module pins 2 9 7 Analog Inputs The Kintex 7 FPGA devices provi...

Страница 20: ...ions and equipped FPGA devices MGT Speed FPGA Device 6 6 Gbit sec FPGA devices of speedgrade 1 or in FBG package 10 3125 Gbit sec FPGA devices of speedgrade 2 in FFG package Table 10 MGT Switching Cha...

Страница 21: ...Power Enable Power Good The Mercury KX2 FPGA module provides a power enable input on the module connector This input may be used to shut down the DC DC converters for 1 0 V 1 2 V 1 5 V 1 8 V and 2 5...

Страница 22: ...3 V voltage regu lators All other supplies are generated from the 3 3 V supply The input current is rated at 3 A 0 3 A per connector pin VCC_BAT A 168 2 0 3 6 V Battery for the RTC and FPGA encryption...

Страница 23: ...tion Note 15 Product Name Package Name Heat Sink Part Number Thermal Pad Part Number Mercury KX2 FBG676 FFG676 20 ATS 52270G C1 R0 TG6050 28 28 1 Table 15 Heat Sink Type Please note that the provided...

Страница 24: ..._L13N_T2_MRCC_33 FPGA_MDIO_EMCCLK 100 MHz B26 IO_L3N_T0_DQS_EMCCLK_14 External configura tion clock Table 17 Module Clock Resources 2 13 Reset The FPGA configuration clear signal FPGA_PROG and the FPG...

Страница 25: ...The DDR3 SDRAM on the Mercury KX2 FPGA module is operated at 1 35 V low power mode or at 1 5 V depending on a selection signal Four 16 bit memory chips are used to build a 64 bit wide memory Note that...

Страница 26: ...dule variant may be used 2 15 2 Signal Description Please refer to the Mercury KX2 FPGA Module FPGA Pinout Excel Sheet 4 for detailed information on the DDR3 SDRAM connections 2 15 3 Termination Warni...

Страница 27: ...e of 1 35 V must be selected in the Memory Interface Generator MIG parameters in Vivado For 1 5 V operation DDR3_VSEL must be set to high impedance not driven logic 1 2 16 QSPI Flash The QSPI flash ca...

Страница 28: ...to program the QSPI flash from an external master Please refer to Section 3 for details on programming the flash memory Warning Special care must be taken when connecting the QSPI flash signals on th...

Страница 29: ...n resistors are disabled at that moment The bootstrap options of the Ethernet PHY are set as indicated in Table 25 Depending on the used IP core configuration of the RGMII delays in the Ethernet PHYs...

Страница 30: ...in synchronous FIFO interface mode or for UART SPI or I2C transfers Please refer to the FTDI device datasheet for details Please note that when using the synchronous FIFO interface in certain temperat...

Страница 31: ...CLK CCLK_0 C8 SCK A 118 10 k pull up IO_0_14 K21 to VCC_CFG_B14 FLASH_CS IO_L6P_T0_FCS_B_14 C23 CS A 116 10 k pull up to VCC_CFG_B14 FLASH_DI IO_L1P_T0_D00_MOSI_14 B24 SI IO0 A 114 10 k pull up to VCC...

Страница 32: ...outed to module connector C are supplied with the voltages provided by the user when C_PRSNT is low or with a default voltage of 1 8 V when C_PRSNT is unconnected C_PRSNT is equipped with a 4 7 k pull...

Страница 33: ...f the I O signals during power up Figure 12 indicates the location of the pull up pull down resistors on the module PCB lower right part on the top view drawing Figure 11 Pull Up During Configuration...

Страница 34: ...B14 It is recommended to add 22 series termination resistors between the module and the JTAG header close to the source Please refer to the Enclustra Module Pin Connection Guidelines for details on JT...

Страница 35: ...transmitted from an external device to the FPGA The configuration pins of the FPGA are connected directly to the module connector allowing the configuration of the FPGA from a microcontroller or anot...

Страница 36: ...PI Master The signals of the QSPI flash are directly connected to the module connector for flash access As the flash signals are connected to the FPGA device as well the FPGA device pins must be tri s...

Страница 37: ...to transfer data between the FPGA and the USB master The selected configuration is controlled by an FTDI general purpose I O refer to Table 34 for details Port B of the FTDI is used to access the modu...

Страница 38: ...PROG must be pulled to ground For the slave serial configuration FPGA_MODE must be pulled high or left open while for master serial configuration FPGA_MODE must be pulled low On revision 1 modules the...

Страница 39: ...ing via FTDI Table 37 lists the FTDI signals for QSPI flash programming FTDI Port Connection Direction Static Value Description BDBUS0 FLASH_CLK Out QSPI flash configuration clock BDBUS1 FLASH_DI Out...

Страница 40: ...he QSPI flash on the Mercury KX2 FPGA module can be programmed via FTDI using the Enclustra Module Configuration Tool MCT 14 Slave serial configuration is also supported by the Enclustra MCT software...

Страница 41: ...scribes the signals of the I2C interface All signals have on board pull up resistors to VCC_3V3 All signals must be connected to open collector outputs and must not be driven high from any source I2C_...

Страница 42: ...p Address Length bits Description 0x00 32 Module serial number 0x04 32 Module product information 0x08 32 Module configuration 0x0C 32 Reserved 0x10 48 Ethernet MAC address 0x16 48 Reserved 0x1C 32 Ch...

Страница 43: ...flash memory size MB 0 0 MB 7 64 MB Resolution 1 MB Table 42 Module Configuration The memory sizes are defined as Resolution 2 Value 1 e g DRAM 0 not equipped DRAM 1 8 MB DRAM 2 16 MB DRAM 3 32 MB et...

Страница 44: ...s Table 45 indicates the recommended operating conditions for Mercury KX2 FPGA module The values given are for reference only for details please refer to the Kintex 7 Datasheet 18 Symbol Description R...

Страница 45: ...tra online request order form for ordering or requesting information http www enclustra com en order 6 2 Support Please follow the instructions on the Enclustra online support site http www enclustra...

Страница 46: ...acteristics on the Mercury KX2 FPGA module 20 11 Generated Power Supplies 21 12 Module Power Status and Control Pins 21 13 Voltage Supply Inputs 22 14 Voltage Supply Outputs 22 15 Heat Sink Type 23 16...

Страница 47: ...0 EEPROM Sector 0 Memory Map 42 41 Product Information 42 42 Module Configuration 43 43 FPGA Device Types 43 44 Absolute Maximum Ratings 44 45 Recommended Operating Conditions 44 D 0000 430 002 47 48...

Страница 48: ...uidelines Ask Enclustra for details 11 Enclustra Mercury Master Pinout Ask Enclustra for details 12 Hirose FX10 Series Product Website http www hirose connectors com 13 Mercury PE1 User Manual Ask Enc...

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