Emerson 6806800M67H, Инструкция по установке и эксплуатации

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Functional Description
ATCA-F140 Installation and Use (6806800M67H )
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This external interrupt is steered through the PIC of P2020 QorIQ Integrated Processor to
the IRQ_OUT signal.
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The IRQ_OUT signal from the interrupt controller is then automatically detected by the
DDR controller, which immediately causes main memory to enter self-refresh mode.

1ms after the interrupt signal (IRQ_L[11]) the FPGA asserts the reset signal for at least
50ms.
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Read persistent memory bit in FPGA.
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Initialize main memory but do not clear persistent memory area.
4.4 IPMI
The IPMI function of the ATCA-F140 is implemented using the Emerson common ATCA base
IPMI design. This building block is based on the Pigeon Point Systems IPMI implementation
using the Renesas HD64F2166 microcontroller which is part of the H8S controller family. The
IPMI building block implementation provides the following features:

Two IPMB interfaces to the backplane
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One local IPMB interface for onboard IPMI

One I2C/IPMB interface for intelligent or non-intelligent RTMs

One private I2C interface for non-intelligent I2C devices
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Serial UART (SIPL) and KCS/LPC interfaces to the P2020 service processor
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Analog voltage sensor inputs
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Service processor boot flash fall over selection
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Watch-dog timer
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