ELiiXA® UC8/UC4
23
Eliixa_Color–revF 04/11
e2v semiconductors SAS 2011
6.3.2
Output modes and Spatial Rebuild
•
Signal source
:
Defines if the data comes from the Sensor or the FPGA (test Pattern). This command is
available in the CommCam “Setup” section :
Ö
Read function : “
r srce
”;
Return by the camera: “0” if Source from the Sensor and “1” if test pattern active
Ö
Write function : “
w srce
” <value> :
“0” to switch to CCD sensor image
“1” to switch to Test Pattern.
The Test pattern is a single ramp. The detail of this test pattern is given in
APPENDIX B.
The test pattern is generated in the FPGA : It’s used to point out any interface
problem with the Frame Grabber.
The test pattern is generated by the FPGA. This is a 12bit width pattern identical for each line as following:
R
G
B
Nir
0 80
40 C0
1
81
41
C1
2
82
42
C2
3
83
84
C3
… … … …
… … … …
… … … …
F00 F80 F40 FC0
F01 F81 F41 FC1
… … … …
… … … …
F3F FBF F7F FFF
F40 FC0 F80 FFF
… … … …
… … … …
FFD
FFF
FFF
FFF
FFE
FFF
FFF
FFF
FFF FFF FFF FFF