E.F. Johnson Company 242-20X1-213, Руководство пользователя

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CIRCUIT DESCRIPTION
6-30
August 2000
Part No. 001-2001-200
Microprocessor U13 is an 8052 that uses external
EPROM (Erasable Programmable Read Only Mem-
ory) U14, an 8-bit device that stores the program. The
microprocessor uses 2k x 8 EPROM and 64k x 8
RAM. The RAM (Random Access Memory) is used
for temporary data storage. The HSDB processor is
configured by the Main Processor.
The internal data bus of the microprocessor has
four input/output ports. These ports have eight lines
each, giving a total of 32 input/output lines. These
ports are designated P0, P1, P2, P3. P0 is used as a
data bus. Ports P1 and P2 are always used as general
purpose inputs/outputs. P3 is used for specialized
functions, i.e. a serial port (RxD/TxD) and interrupt
(INT).
The operating speed of the microprocessor is set
by an 11.059 MHz clock generated by Y2. This clock
frequency is divided down by an internal divider to
provide a machine cycle time of 1.08
µ
s. Most pro-
gram instructions are executed in one machine cycle
and none require more than four machine cycles.
The microprocessor U13 communicates with the
main processor (U27) through U9 and U10. U9 is a
Transmit FIFO (First In First Out) and U10 is a
Receive FIFO. This combination makes up an asyn-
chronous parallel-to-parallel interface to the Main
Processor.
Microprocessor U13 also calculates the current
system priority for the channel. This priority is from
the programming software responses and the current
priority is sent to the main processor. U13 also reads
repeater number and channel number information in
memory. U13 also determines the current free
repeater and includes that information in the data sent
to the Main Processor.
6.9.4 CHIP SELECT DECODERS (U15/U4)
Chip select decoders select the peripheral chip to
read from or write to.
6.9.5 P1 SIGNAL CONNECTOR
This is the signal interface connector P1 (64 pin)
that connects the Address and Data buses and control
lines to the backplane connector.
Pins 1-10 ADDRESS BUS
Pins 33-42
This provides a path between the MPC main pro-
cessor and the external memory on the MPC and the
other cards in the Controller. This bus retrieves infor-
mation programmed into memory for the operation of
the repeater.
Pins 11-14 DATA BUS
Pins 43-46
The data bus provides a means of transferring
data to and from the CPU on the MPC, memory stor-
age on each card and peripheral devices in and out of
the MAC and IAC.
Pin 15 MREQ
MREQ is a memory request line operates in con-
junction with the Read/Write lines. These provide the
ability to read from or write to the main processor
memory on the MPC.
Pin 16 MSTB
MSTB is a memory strobe line used during MPC
main processor Read/Write operations to external
memory on the MPC and other cards plugged into the
backplane.
Pins 17-20 UNUSED
Pin 21 LPTT
The Logic Push-To-Talk is an open collector
from the Controller. It has a sink capability of 20 mA
and a maximum voltage rating of 18V. The transmit-
ter should produce power when this pin is a logic low.
Transmit indicator is on the IAC and is controlled
independently of the LPTT.
Pins 22-23 UNUSED
Pins 24/56 HSDB+/HSDB-
This interconnects all repeaters to provide an
exchange of information. This control technique is
called distributive processing and eliminates a sepa-
rate system controller at each site. Information on this