Hardware and Software Design • Manufacturing Services
page 31
Clock Select : When 0 the PCI clock is used instead of the de-serializer clock. When 1 the de-serializer clock is
used. Select the PCI clock to use the load FIFO mode. To fill a specific value into all of SDRAM, write the value to
the holding register, select the PCI clock, and start a capture with X set to max size and the memory controller
set to have the channel selected start at 0 and occupy the entire space. The data is muxed into the pipeline at the
last stage when the select bit is ‘0’ and the Count enable bit is ‘0’.
Count Enable: When ‘1’ enables the 12 bit counter to count. When the PCI clock is selected then the counter
output is muxed into the data stream prior to word building. If the tag bits are set to 0xff, the continuous mode
selected, start bit set [0x4cff] then the counter data will be inserted into the data stream and the state-machine
will not add the parity leaving the counter output as the data stream. The count is pre-loadable. The pipeline will
absorb the first few counts. Starting with 0x000 preloaded will yield 0x00040003 loaded into the Input FIFO.
De-serializer enable : When ‘0’ the de-serializer is in power down mode. When ‘1’ the de-serializer is enabled. The
de-serializer should be enabled prior to selecting the de-serializer clock. The PLL in the deserializer takes 10 mS
to stabilize assuming there is an active clock reference on the serial input. There must be a delay after enabling
the channel before starting a capture. The de-serializer cable can be detected as active by reading the X Total
counter back while the data is being captured. If the counter is not progressing then there is no reference clock.
Select all patterns for start and save to keep the counter responding to each clock that is received.
Tag Mask : When ‘0’ the tag bits are forced to ‘0’ for storage purposes only. The tag bits are still used to
determine which samples to start and save. ‘1’ corresponds to saving the tag bits.