Hardware and Software Design • Manufacturing Services
page 17
mt_xn is active low. ‘0’ – FIFO is empty
hf_xn is active low ‘0’ – FIFO is half full or more
ff_xn is active low ‘0’ – FIFO is full.
0 corresponds to channels 0-3, and 1 to channels 4-7.
Done channel X when 1 is done meaning that the requested samples have been transferred. The Data has been
captured and stored into SDRAM, or read from SDRAM to the output FIFO as programmed. The done bits are
cleared by writing a ‘1’ to the corresponding position. The done bits are used to create an interrupt to the host if
the corresponding interrupt enable bit is set. The bits should be cleared after the Xilinx’s are enabled from reset
to clear any transition induced status changes.
FIFO_X_Err when ‘1’ indicates that the Output FIFO for that channel has become full at some point. In Retrieve
mode this is not a problem. In Direct mode this is an overflow error. Clear by writing with the corresponding bit
set to ‘1’.
SW7-0 reflect the settings of the user defined dip-switch on the board. It is envisioned that the switch is used as a
board level “address” to identify a specific slot and cable with a particular device number.
DMA FIFO Holding Register Target Read
$0438
Bit#
Definition
31-0
Output FIFO data
Read the data stored within the Output FIFO. Select the Output FIFO to read with the Channel definition. Enable the
process with READ_EN_STD. When the valid bit is set, data is stored into the FIFO Holding Register. The data is
automatically updated when a read is detected. The hardware overlaps the read of the FIFO and update of the
register to reduce the access time from the PCI bus. If the FIFO has data to read, the next data will be available
immediately. The valid bit should be used to verify that the first data is available.
