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Hardware and Software Design • Manufacturing Services

page 18

DMA FIFO Holding Register DMA Read

$2XXX

Bit#

Definiti

on

31-0

Output FIFO data

Read the data stored within the Output FIFO. Select the Output FIFO to read with the Channel definition. Enable the
process with READ_EN_DMA. When enabled and a read to this address occurs the DMA engine within the Xilinx is
started. The data is read from the FIFO, stored within the Input FF register and then moved to the Holding register
– a three deep pipeline. The initial READY signal is held off until data is ready to be read from the holding register.
The data within the register is updated on each clock until the BLASTn signal is asserted by the PLX device.
BLASTn will be asserted when the Burst transfer to the PCI bus is halted due to length of transfer or software
intervention.

The PLX device requires about 6 clocks to arbitrate for the bus and start the transfer. The max time permitted
for a transfer is 256 clocks leaving about 250 data transfers per burst. The transfer is interrupted with the
BLASTn signal and the pipeline retains the current contents. The next transfer will begin with the data within the
pipeline [shorter start-up sequence within the DMA Xilinx as no prefetch and pipeline fill are required on a restart.
In Direct mode, the PLX device will likely have to wait for the DMA process to start-up as the Output FIFO reads
happen at a faster rate than the input data from the LVDS front end. During the Process the software should not
attempt to access the PCI_LVDS_8R. During Retrieve mode, the Address Generator will stay ahead of the DMA
operation; the Output FIFO will always be ready to start a new transfer.

The DMA transfer is controlled by the scatter gather list, PLX device, Address Generator and DMA Xilinx. All
must be properly coordinated for effective operation. The Scatter Gather list instructs the PLX where to place
data and how much, when to interrupt and when it is completed. The DMA Xilinx selects the group of channels to
read from and DMA mode. The Address Generator has a programmed length and address offset to use to define
the data to read. The length programmed is in 64 bit words and must be set to provide all of the data requested
by the scatter gather list. The scatter gather list will reduce the size of each DMA action and the PCI bus
requirements will further subdivide the transfers to be the actual PCI transfers.

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Содержание LVDS 8R

Страница 1: ...e product described in this document at any time and without notice Furthermore Dynamic Engineering assumes no liability arising out of the application or use of the device described herein The electronic equipment described herein generates uses and can radiate radio frequency energy Operation of this equipment in a residential area is likely to cause radio interference in which case the user at ...

Страница 2: ...s 20 Address Generator SDRAM Start Address Registers 20 Address Generator SDRAM Length Registers 21 Address Generator SDRAM Control Registers 22 Address Generator SDRAM Base Control Registers 25 Address Generator SDRAM Status Registers 27 FE Definitions 29 FE Tag Bit Definition Registers 29 FE X Stop Registers 32 FE Y Stop Registers 32 FE Z Stop Registers 33 FE X Total Counter Read back 33 FE Data...

Страница 3: ...ices page 3 Operational Brief 37 LVDS Connector Definition 40 Construction and Reliability 43 Thermal Considerations 43 Warranty and Repair 43 Service Policy 44 Out of Warranty Repairs 44 For Service Contact 44 Specifications 45 Order Information 46 ...

Страница 4: ... The data is read from the Input FIFO by the Latch Xilinx and either written to the SDRAM or to the Output FIFO The data is read into the Latch Xilinx at 66 MHz and written to the SDRAM at 33 MHz The data width is doubled from 32 bits to 64 bits in this path The Data can also be read from the SDRAM and written to the Output FIFO When data is written to the Output FIFO the width is 32 bits and the ...

Страница 5: ...the software to load data words into the Input FIFO directly The FE design also has a 12 bit counter that can be used to load data automatically into the FIFO for performance testing The Counter inserts data at 33MHz into the data path to provide a continuous data stream The counter can be used to cause Direct or Capture mode operations Retrieve can be used after capture to read the data back for ...

Страница 6: ...6 MB 1K x 32 DMA Xilinx Add Gen Xilinx LVDS IF LVDS IF LVDS IF LVDS IF SDRAM 32 1K x 32 LAT Xilinx 256 MB LVDS IF LVDS IF LVDS IF LVDS IF FIFO FIFO FIFO FIFO SDRAM 64 FIFO 32 256 MB Add Gen Xilinx LVDS IF LVDS IF SDRAM 64 32 256 MB 1K x 32 PLX 9054 PCI 33 32 FIFO FE Xilinx FE Xilinx FE Xilinx FE Xilinx LAT Xilinx Control Bus ...

Страница 7: ...PLX 9054 internal register The Interrupt must be enabled within the PLX for the interrupts described within this document to reach the host Please download the PLX 9054 manual for complete details Front End Filter Channels 0 1 Decode number Address offset Chip Definition 0 0000 FE01 TAG_DEF_0 0004 FE01 X0_STOP 0008 FE01 X1_STOP 000C FE01 Y0_STOP 0010 FE01 Y1_STOP 0014 FE01 Z0_STOP 0018 FE01 Z1_STO...

Страница 8: ... 0040 FE23 TAG_DEF_2 0044 FE23 X2_STOP 0048 FE23 X3_STOP 004C FE23 Y2_STOP 0050 FE23 Y3_STOP 0054 FE23 Z2_STOP 0058 FE23 Z3_STOP 005C FE23 X_TOTAL_2_RDBK 0060 FE23 X_TOTAL_3_RDBK 0064 FE23 2 3_DTA_PAT 0068 FE23 FIFO_2 WRT 006C FE23 FIFO_3 WRT 0070 FE23 TAG_DEF_3 0074 FE23 FE_DONE_2 0078 FE23 FE_DONE_3 007C FE23 Preload data counter 2 3 ...

Страница 9: ... ADD CH 0 0084 ADD0_3 Start ADD CH 1 0088 ADD0_3 Start ADD CH 2 008C ADD0_3 Start ADD CH 3 0090 ADD0_3 Length CH 0 0094 ADD0_3 Length CH 1 0098 ADD0_3 Length CH 2 009C ADD0_3 Length CH 3 00A0 ADD0_3 CNTL CH 0 00A4 ADD0_3 CNTL CH 1 00A8 ADD0_3 CNTL CH 2 00AC ADD0_3 CNTL CH 3 00B0 ADD0_3 SDRAM Base 0 3 00B4 00B8 ADD0_3 Spare 00BC ADD0_3 Status 0 3 3 spare ...

Страница 10: ...P 011C FE45 X_TOTAL_4_RDBK 0120 FE45 X_TOTAL_5_RDBK 0124 FE45 4 5_DTA_PAT 0128 FE45 FIFO_4 WRT 012C FE45 FIFO_5 WRT 0130 FE45 TAG_DEF_5 0134 FE45 FE_DONE_4 0138 FE45 FE_DONE_5 013C FE45 Preload data counter 4 5 Front End Filter Channels 6 7 Decode number Address offset Chip Definition 5 0140 FE67 TAG_DEF_6 0144 FE67 X6_STOP 0148 FE67 X7_STOP 014C FE67 Y6_STOP 0150 FE67 Y7_STOP 0154 FE67 Z6_STOP 01...

Страница 11: ...r Channels 4 7 Decode number Address offset Chip Definition 6 0180 ADD4_7 Start ADD CH 4 0184 ADD4_7 Start ADD CH 5 0188 ADD4_7 Start ADD CH 6 018C ADD4_7 Start ADD CH 7 0190 ADD4_7 Length CH 4 0194 ADD4_7 Length CH 5 0198 ADD4_7 Length CH 6 019C ADD4_7 Length CH 7 01A0 ADD4_7 CNTL CH 4 01A4 ADD4_7 CNTL CH 5 01A8 ADD4_7 CNTL CH 6 01AC ADD4_7 CNTL CH 7 01B0 ADD4_7 SDRAM Base 4 7 01B4 01B8 ADD4_7 Sp...

Страница 12: ...e and Control Decode number Address offset Chip Definition 10 0400 DMA Base Control r w 0404 0408 040C 0410 0414 0418 041C 0420 0424 0428 042C 0430 0434 DMA Xilinx Status Read 0438 DMA FIFO data slave read 043C DMA Status read DMA Status Clear write 2XXX DMA Data Read 11 7F spare ...

Страница 13: ... Read Write Bit Definition 0 Reset_0 1 Reset_1 2 Reset_2 3 Reset_3 4 Reset_4 5 spare 6 spare 7 LED Control 8 READ_EN_STD 9 READ_EN_DMA 10 Channel 15 11 spare 16 Int En 0 17 Int En 1 18 Int En 2 19 Int En 3 20 Int En 4 21 Int En 5 22 Int En 6 23 Int En 7 24 Master Interrupt Enable 25 Force Interrupt ...

Страница 14: ...e reset after the Latch devices are enabled to prevent spurious writes to the FIFO when the Latch Xilinx starts up Int En X When set 1 and the corresponding Done bit is received the interrupt to the host is asserted via the PLX device The PLX will also have to be enabled to cause an interrupt The master interrupt within the DMA Xilinx will need to be enabled Clear the interrupt by clearing the don...

Страница 15: ...FIFO debth is 1K Starting with 1 2 FIFO guarantees that the FIFO will not run dry during a burst transfer Channel 0 and 4 are used to Retrieve data When channel 0 or 4 reaches the Done condition so that all requested data is stored into the FIFO the 1 2 full requirement is waived to allow the DMA counter in the PLX device to complete the transfer and not get stuck needing less than 1 2 FIFO of dat...

Страница 16: ... 0 1 Done channel 1 2 Done channel 2 3 Done channel 3 4 Done channel 4 5 Done channel 5 6 Done channel 6 7 Done channel 7 8 FIFO_0_Err 9 FIFO_1_Err 10 gnd 11 gnd 12 gnd 13 gnd 14 gnd 15 Interrupt RQST 23 16 SW7 0 24 undefined 25 valid 26 mt_out0n 27 hf_out0n 28 ff_out0n 29 mt_out1n 30 hf_out1n 31 ff_out1n ...

Страница 17: ...l has become full at some point In Retrieve mode this is not a problem In Direct mode this is an overflow error Clear by writing with the corresponding bit set to 1 SW7 0 reflect the settings of the user defined dip switch on the board It is envisioned that the switch is used as a board level address to identify a specific slot and cable with a particular device number DMA FIFO Holding Register Ta...

Страница 18: ...ts The next transfer will begin with the data within the pipeline shorter start up sequence within the DMA Xilinx as no prefetch and pipeline fill are required on a restart In Direct mode the PLX device will likely have to wait for the DMA process to start up as the Output FIFO reads happen at a faster rate than the input data from the LVDS front end During the Process the software should not atte...

Страница 19: ...ng Services page 19 DMA Xilinx Status 0434 Bit Definition 0 DN01 1 DN23 2 DN45 3 DN67 4 DNL0 5 DNL1 6 DNA0 7 DNA1 DNx are the done bits from the Xilinx devices After initialization the Done signal should be 1 if a proper load has taken place ...

Страница 20: ...AM is organized as 64 bit words The addresses increment with groups of 8 bytes To select offset 8M bytes the address would be 1M long words With a range of 24 0 the entire 256 Mb address space is selectable by any channel All transfers will start and stop on 64 bit boundaries by hardware definition Smaller transfer requests will be padded to fill a complete word For example if an odd number of sam...

Страница 21: ...ferent combinations of starting finishing and crossing addresses automatically and at full rate as defined in the specification If attempting to operate outside of the specification then pay attention to the boundary conditions to increase performance Pages are 0x00 0x3ff The memory is sufficiently large that the individual sections can be located on page boundaries For performance and maintenance...

Страница 22: ...0A8 ADD0_3 CNTL CH 2 00AC ADD0_3 CNTL CH 3 01A0 ADD4_7 CNTL CH 4 01A4 ADD4_7 CNTL CH 5 01A8 ADD4_7 CNTL CH 6 01AC ADD4_7 CNTL CH 7 Read Write Bit Definition 7 Start for Channel x 6 3 unused undefined mask off for read back 2 IO set to 1 for write to SDRAM 0 for Read 1 DIR set to 0 for SDRAM capture retrieve 1 for Direct 0 Load set to 0 for preload 1 for start with next address Eight registers at d...

Страница 23: ...M to the PCI bus In capture mode any number of channels can be enabled and any combination of addresses and lengths In Retrieve mode only channel 0 or Channel 4 should be active Point the start address at the first channel of interest set the length and start Retrieve mode When the data read is completed move the start pointer to the next selection and start channel 0 Retrieve again The length reg...

Страница 24: ...Hardware and Software Design Manufacturing Services page 24 access and to pre load channel 0 after initialization In Retrieve and Direct mode the pre load control has no affect ...

Страница 25: ...fined state until the initialization bit is set high The SDRAM has an internal register which is controlled by writing to it with the data placed on the address lines Channel 0 has been selected as the initialization source for the data Prior to setting the initialization bit the data 0x27 must be written into the Channel 0 Start register During the initialization cycle the 0x27 will be transferre...

Страница 26: ...detected A counter delays for 256 clocks then a refresh cycle 4 occurs in an endless loop When a command start has been set then the hardware will begin processing that command Any combination of channels can be activated The channels should be activated before the corresponding channels on the Front End Filters in capture mode to make sure that there is not an overflow condition at the Input FIFO...

Страница 27: ...r SDRAM Status Registers 0x00BC ADD0_3 Status 0 3 Bit Definition 0 Done channel 0 1 mt_0n 2 hf_0n 3 ff_0n 4 Done channel 1 5 mt_1n 6 hf_1n 7 ff_1n 8 Done channel 2 9 mt_2n 10 hf_2n 11 ff_2n 12 Done channel 3 13 mt_3n 14 hf_3n 15 ff_3n 16 gnd 17 mt_out0n 18 hf_out0n 19 ff_out0n ...

Страница 28: ...out1n The status register reports the Input FIFO status Done bits from the FE Xilinx and the Output FIFO status mt_xn is active low 0 FIFO is empty hf_xn is active low 0 FIFO is half full ff_xn is active low 0 FIFO is full Done channel X when 1 is done the requested samples have been captured and loaded into that channel s FIFO The Done bits are transitory in nature and should not be used to poll ...

Страница 29: ...FE45 TAG_DEF_4 0130 FE45 TAG_DEF_5 0140 FE67 TAG_DEF_6 0170 FE67 TAG_DEF_7 Read Write Bit Definition 1 0 Tag 0 channel Start Save 3 2 Tag1 channel Start Save 5 4 Tag 2 channel Start Save 7 6 Tag 3 channel Start Save 8 Parity Channel Odd Even 9 Parity Channel On Off 10 Start Channel 11 Continuous mode 12 Clk Sel 13 Tag Mask 14 Count enable 15 Ch A B De serializer enable 31 16 unused undefined ...

Страница 30: ...gister can be written to with the tag parity clock selection de serializer enable and start action The Start bit is set by software to initiate operation and cleared at the end of the sequence programmed The start bit can be polled to see if the data capture has completed at the Filter The start bit can be cleared with software to halt the continuous mode Continuous The mode is determined by the s...

Страница 31: ...and the state machine will not add the parity leaving the counter output as the data stream The count is pre loadable The pipeline will absorb the first few counts Starting with 0x000 preloaded will yield 0x00040003 loaded into the Input FIFO De serializer enable When 0 the de serializer is in power down mode When 1 the de serializer is enabled The de serializer should be enabled prior to selectin...

Страница 32: ... X6_STOP 0148 FE67 X7_STOP Xx Stop Read write 26 0 set the number of samples to capture per X loop FE Y Stop Registers 000C FE01 Y0_STOP 0010 FE01 Y1_STOP 004C FE23 Y2_STOP 0050 FE23 Y3_STOP 010C FE45 Y4_STOP 0110 FE45 Y5_STOP 014C FE67 Y6_STOP 0150 FE67 Y7_STOP Yx Stop Read write 20 0 set the number of samples to skip after capturing X before looping If not in a loop mode then should be set to 0 ...

Страница 33: ...unt from 0 to the value programmed F is 0 through F for a total of 16 program in N 1 to get the count that you desire FE X Total Counter Read back 001C FE01 X_TOTAL_0_RDBK 0020 FE01 X_TOTAL_1_RDBK 005C FE23 X_TOTAL_2_RDBK 0060 FE23 X_TOTAL_3_RDBK 011C FE45 X_TOTAL_4_RDBK 0120 FE45 X_TOTAL_5_RDBK 015C FE67 X_TOTAL_6_RDBK 0160 FE67 X_TOTAL_7_RDBK X Total x Counter Read only Read the total number of ...

Страница 34: ... to write to FIFO Can be written once to the register then loaded multiple times or re written to a new value for each FIFO write The data is muxed into the data pipeline when the PCI clock is selected The PCI clock needs to be selected to have proper operation when writing directly to the FIFO FE Data Write Register 0028 FE01 FIFO_0 WRT 002C FE01 FIFO_1 WRT 0068 FE23 FIFO_2 WRT 006C FE23 FIFO_3 W...

Страница 35: ...be sent to the Address generator for that channel The Done bit will signal the completion of an operation Useful to force completion Example load data with software data definition and load commands into the FIFO Start up the Address generator to move in direct mode to the Output FIFO Set the Done bit to cause the Address generator to read the last portion of data from the Input FIFO Use the bit t...

Страница 36: ...d the counters with the start pattern The lower Channel A counter will be loaded with the 11 0 data bits and the upper channel B will be loaded from 27 16 The counters when enabled will start to count from this pattern The load function has higher priority than the count function A write while already enabled will reset the counter to the written value for one clock then counting will begin again ...

Страница 37: ...d Software Design Manufacturing Services page 37 Operational Brief lvds_fe input FIFO lvds_lat SDRAM lvds_add output FIFO Direct Retrieve REn OEn WEn WEn Status Address Control Control Xilinx Xilinx Xilinx Capture ...

Страница 38: ...and written to the output FIFO Data is transferred 256 long words to a burst The state machine will keep from just under 1 2 full to full in the output FIFO by monitoring the HF flag and bursting when there is room The DMA controller will attempt to empty the FIFO to the PCI bus at the same time The Address generator has the advantage of 2X bandwidth and will be able to keep the DMA process from r...

Страница 39: ... uS to capture enough samples to cause overflow once the FE is enabled 1 2 1 at input FIFO all but one in output FIFO 2 samples per word 25 mhz capture rate There is plenty of time for the PLX to fetch the 4 parameters from main memory and to start up in time to transfer the data The PLX device should be programmed to start the DMA transfer with the first sample read from the DMA Xilinx and to rea...

Страница 40: ...LK_T 11 CH6RXCLKM 06_CLK_C 12 CH6RX2P 13 CH6RX2M 14 CH6RX1P 06_UDATA_T 15 CH6RX1M 06_UDATA_C 16 CH6RX0P 06_LDATA_T 17 CH6RX0M 06_LDATA_C 18 GND 19 GND 20 CH4RXCLKP 04_CLK_T 21 CH4RXCLKM 04_CLK_C 22 CH4RX2P 23 CH4RX2M 24 CH4RX1P 04_UDATA_T 25 CH4RX1M 04_UDATA_C 26 CH4RX0P 04_LDATA_T 27 CH4RX0M 04_LDATA_C 28 GND 29 GND 30 CH1RXCLKP 01_CLK_T 31 CH1RXCLKM 01_CLK_C 32 GND ...

Страница 41: ... GND 41 CH0RXCLKP 00_CLK_T 42 CH0RXCLKM 00_CLK_C 43 CH0RX2P 44 CH0RX2M 45 CH0RX1P 00_UDATA_T 46 CH0RX1M 00_UDATA_C 47 CH0RX0P 00_LDATA_T 48 CH0RX0M 00_LDATA_C 49 GND 50 GND 51 60 SPARE 61 CH7RX0M 07_LDATA_C 62 CH7RX0P 07_LDATA_T 63 CH7RX1M 07_UDATA_C 64 CH7RX1P 07_UDATA_T 65 GND 66 CH7RX2M 67 CH7RX2P 68 CH7RXCLKM 07_CLK_C 69 CH7RXCLKP 07_CLK_T 70 GND 71 GND 72 CH5RX0M 05_LDATA_C ...

Страница 42: ...80 GND 81 GND 82 CH3RX0M 03_LDATA_C 83 CH3RX0P 03_LDATA_T 84 CH3RX1M 03_UDATA_C 85 CH3RX1P 03_UDATA_T 86 CH3RX2M 87 CH3RX2P 88 CH3RXCLKM 03_CLK_C 89 CH3RXCLKP 03_CLK_T 90 GND 91 GND 92 CH2RX0M 02_LDATA_C 93 CH2RX0P 02_LDATA_T 94 CH2RX1M 02_UDATA_C 95 CH2RX1P 02_UDATA_T 96 CH2RX2M 97 CH2RX2P 98 CH2RXCLKM 02_CLK_C 99 CH2RXCLKP 02_CLK_T 100 GND GND AC DC Open connection to Ground Standard open ...

Страница 43: ...st chassis very minimal air flow will be required The airflow required will be a function of the temperature of the cooling air and the amount of heat to dissipate from the PCI_LVDS_8R and the other cards installed into the same chassis Warranty and Repair Dynamic Engineering warrants this product to be free from defects in workmanship and materials under normal use and service and in its original...

Страница 44: ...f a technical contact For out of warranty repairs a purchase order for repair charges must accompany the return Dynamic Engineering will not be responsible for damages due to improper packaging of returned items For service on Dynamic Engineering Products not purchased directly from Dynamic Engineering contact your reseller Products returned to Dynamic Engineering for repair by other than the orig...

Страница 45: ...isters Status Registers Initialization Hardware Reset forces all registers to 0 Access Modes DMA and target Interrupt Programmable interrupt based on each separate channel Onboard Options All Options are Software Programmable Interface Options 3M LVDS Connector MDR Series 100 pin Dimensions Standard Full Length PCI Card Construction FR4 Multi Layer Printed Circuit Through Hole and Surface Mount Co...

Страница 46: ...et operation Universal voltage 32 bit 33 MHz PCI interface 3 3V power supply utilized 1 Same as no dash version plus on board regulator used to convert 5V to 3 3 Tools for PCI_LVDS_8R Engineering Kit PDF of schematic Reference Software including C source that we use for testing the design NT WinRT environment LVDS Cable MDRterm100 LVDS breakout connector with testpoints Driver Windows NT compatibl...

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