Hardware and Software Design • Manufacturing Services
page 30
Two registers at different offsets with the same bit definitions provided for the A and B channels.
Tag Bit definitions : The tag bits are received from the de-serializer as part of the data stream. The received tag
bits are decoded using the definitions in the base register. For example if a tag pattern of ‘00’ is received then
bits 1,0 are used to determine if the data should be saved or not and if the pattern is a start pattern or not. Each
tag pattern, 0,1,2,3 is defined separately for each channel. Any number of tag patterns can be marked for start
and storage. $FF would correspond to no filtering with all set for start and save. $00 would correspond to no
action as no start bit is selected and no data set for storage. A more normal situation would be to select a subset
of patterns for start and storage. Please note that the start pattern is not saved unless it is marked to be saved.
Parity : The parity is programmable to be odd or even and to be inserted or not. The odd data bits
[1,3,5,7,9,11,13] are used to determine the parity generation for bit 15. The even parity bits are used to
determine the parity generation for bit 14. If parity is not enabled then ‘0’ is inserted in the parity bit locations.
Start : once the stop values are set the base register can be written to with the tag, parity, clock selection, de-
serializer enable and start action. The Start bit is set by software to initiate operation and cleared at the end of
the sequence programmed. The start bit can be polled to see if the data capture has completed at the Filter. The
start bit can be cleared with software to halt the continuous mode.
Continuous : The mode is determined by the stop values programmed and the Continuous bit. If the Continuous bit
is set then the stop values are ignored and all programmed values are captured. If all values are desired then $FF
should be programmed into the mode bit definitions. The mode is halted by resetting the start bit. It is
recommended to use the continuous mode for all non-XYZ mode captures and to use the length counter in the
Address generator to control the amount of data captured. In X-Y-Z mode the length of the programmed data
captured by the FE chip should be greater or equal to the amount programmed into the Address generator length
for that channel. If a smaller amount of data is provided by the FE chip then the Address Generator will pad the
data out to the length requested. The done bit will be set by the FE chip when the XYZ sequence is completed and
the Address Generator will interpret that to mean that the last of the data is in the FIFO and read it all out. If the
FIFO becomes empty the Address Generator will re-read the last sample from the FIFO until it completes the
capture operation. Usually this is not what is intended.
