DRS WJ-8611, Инструкция по установке, эксплуатации и обслуживанию

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WJ-8611 DIGITAL VHF/UHF RECEIVER
REMOTE CONTROL 4-27
Table 4-5. Event Summary Register, Bit Evaluation
Bit Mnemonic Description
00 OPC Operation Complete - This bit is set on the
completion of an operation that has been
designated by the *OPC command.
01 Not Used
02 QYE Query Error - Set on an attempt to read data
from the output buffer with no data pending,
or on output buffer overflow.
03 DDE Device Dependent Error - This bit is set when
one or more bits in the Device-Dependent
Error Register is set and reporting is enabled
by the Device Dependent Error Enable
Register.
04 EXE Execution Error - This bit is set when an out
of range argument is sent with a valid
message header or when a valid message can
not be executed due to a device error
condition.
05 CME Command Error - This bit is set when an
unrecognized message header is received.
06 Not Used
07 PON Power On - This bit is set during the
receiver’s power-up sequence. It is also set
when a Device or Selected Device Clear
message is received.
4.6.3 RECEIVER STATUS REGISTER
The Receiver Status Register allows the occurrence of specific operational
events to be reported to the Status Byte Register when enabled by
associated bits of the Receiver Status Enable Register. The status of this
register discloses the reason for the RSB bit of the Status Byte Register to
be set. The *RSR? reads the latched contents of this register and clears the
register. It is also cleared by a *CLS command.
Table 4-6 describes the
bit evaluation of the Receiver Status Register.
Courtesy of http://BlackRadios.terryo.org