DRS WJ-8611, Инструкция по установке, эксплуатации и обслуживанию

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WJ-8611 DIGITAL VHF/UHF RECEIVER
5-14 CIRCUIT DESCRIPTIONS
The Control Processor section maintains control over all receiver
operations. It consists of an MC 68331 16-bit microprocessor,
Programmable Flexible Logic circuits, and a dedicated MC 68HC711D3
gain control microprocessor. This section sends control data to the RF
Tuner Assembly (A3) by way of a serial control bus, down-loads the
operating programs for the two DSP processors, via the 16-bit data bus
contained on the Digital Control PC Assembly (A2), and provides a
control interface to communicate with the receiver’s front panel controls
and rear panel RS-232 Serial or IEEE-488 Parallel interfaces. It also
configures the two programmable Flexible Logic integrated circuits that
provide the interfacing logic between the various digital processing
circuits. On receiver power up, the control processor configures the two
programmable Flexible Logic integrated circuits that provide the
interfacing logic between the various digital processing circuits. It then
downloads the operating programs for the two DSP processors, and sends
receiver parameter data to the DSP Processors. The DSP processors then
use this data to determine the processing tasks associated with signal
conditioning and demodulation of the intelligence.
Two DIP switches (S1 and S2), contained in the Control Processor section,
permit the WJ-8611 Receiver to be configured for its intended operating
environment. On receiver power up, the control processor reads these
switches to determine the operating configuration of the receiver. Switch
S2 selects the default configuration of the receiver’s remote interface. It
selects the type interface that will be active (IEEE-488 or RS-232) and
determines the receiver’s IEEE-488 bus address or the RS-232 baud rate.
When the IEEE-488 mode is selected, the bus address can be set to a value
of from 0 to 30, using switch positions 1 to 5. In the RS-232 mode, the
9600-baud rate or a user-defined baud rate can be selected by switch
position 8 (the user-defined baud rate defaults to 38400 baud unless
otherwise configured). Switch position 7 determines which of the
interfaces will be selected.
Switch S1 determines the operating mode that the receiver assumes at
power up and enables or disables front panel control of the receiver’s
IEEE-488 address selection. Switch position 1 determines if the receiver
powers up in the normal operating mode (switch closed) or if the
configuration mode is active (switch open). Position 6 of S1 permits the
receiver’s IEEE-488 address to be changed at the front panel (switch
closed). If this switch is open, address changes can only be performed at
DIP switch S2.
Table 5-5 provides a summary of the S1 and S2 switch
configurations.
Control over the RF Tuner Assembly (A3) operations is maintained by the
serial control bus, consisting of the RFB CLK, RFB DATA, and RFB STB
serial data and timing lines (J1, pins 19, 20, and 21), and the RFB A0, RFB
A1, and RFB A2 parallel control lines (J1, pins 23, 24, and 25). These
lines provide the data for synthesizer tuning and preselector band selection.
It also controls the tuning of the Tracking Preselector in the RF Tuner
Assembly (A3) via the preselector tuning voltage line PRETV (J1 pin 10).
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