Dewetron DEWE-ORION-0824-20 Series, Техническое справочное руководство

Страница: 41 / 64

Page 41
DE-M080801E • DEWE-ORION-0824-20x • Technical Reference Manual • Printing version 1.1.2 • March 19, 2014
DEWE-ORION-0824-20x
To set nearly each frequency a low jitter programmable PLL (phase locked loop) circuit is used for generating
the clocking frequency. PLL gives the best solution for variable frequency setting with small steps between
the frequency. But still not every frequency is possible to set. The formula below gives you an idea how the
frequency can be set to get different sample rates:
12.8 MHz
Q
1
N
1
OC
. P . .
where Q is limited from 2 to 51; P is limited from 8 to 1600 and N is limited from 1 to 127. OC for fs 1kS/s
<= 51.2 kS/s equals 1024 and for higher sample rates it is fixed to 256. Also the product of 12.8 MHz/Q *
P has to be in the range of 100 to 400 MHz for stable operation. The factors Q, P and N are integer values
and automatically set the best performance values. The table below give a rough idea about the sample rate
resolution at different sample rates.
Sample rate
Resolution [ppm] Resolution [Hz]
1kS/sec 40 0,04 Hz
10kS/sec 70 0,7 Hz
50kS/sec 400 20 Hz
100kS/sec 400 40 Hz
200kS/sec 400 80 Hz
The exact value of the sample is read back (and displayed in DEWESoft) for knowing the exact sample rate.
The factors Q, P and N are integer values and automatically set the best performance values. The exact
value of the sample is read back (and displayed in DEWESoft) for knowing the exact sample rate.
All channels have to be acquired with the same saple rate. It is not possible to set different sample rates to
some channels.
3.1.6 Output data format
Due to the nature of the PCI Bus, each channel is transferred as a 32-bit value, although the converter
output is only a 24-bit value. Multiple channel applications with high sample rates may limit the maximum
sample rate. A 128 channel system with 100 kS/s will give a total output data stream of 51.2 MByte/sec.
23 16 15 8 7 0
23 16 0 0 0 0 0 0 0 0 15 8 7 0
ADC-data (24-bit)
MSB LSB
Transferred data (32-bit) filled with “0”
MS LSB
To reduce this high amount of data by half, a 16-bit mode is implemented. This 16-bit mode will only
transfer 16 bits per ADC. Due to the selection of most significant 16 bits of the 24-bit ADC value, it is also
possible to define the interesting array of bits which should be transferred. That means you have a kind of
programmable range, using this packed mode.