Option
Description
Logical Processor
Enables or disables the logical processors and displays the number of logical processors. If this option is set to
Enabled
, the BIOS displays all the logical processors. If this option is set to
Disabled
, the BIOS displays only one
logical processor per core. This option is set to
Enabled
by default.
CPU Interconnect
Speed
Enables you to govern the frequency of the communication links among the processors in the system.
NOTE:
The standard and basic bin processors support lower link frequencies.
The options available are
Maximum data rate
,
10.4 GT/s
, and
9.6 GT/s
. This option is set to
Maximum data rate
by default.
Maximum data rate indicates that the BIOS runs the communication links at the maximum frequency supported by
the processors. You can also select specific frequencies that the processors support, which can vary.
For best performance, you should select
Maximum data rate
. Any reduction in the communication link frequency
affects the performance of non-local memory accesses and cache coherency traffic. In addition, it can slow access
to non-local I/O devices from a particular processor.
However, if power saving considerations outweigh performance, you might want to reduce the frequency of the
processor communication links. If you do this, you should localize memory and I/O accesses to the nearest NUMA
node to minimize the impact to system performance.
Virtualization
Technology
Enables or disables the virtualization technology for the processor. This option is set to
Enabled
by default.
Adjacent Cache
Line Prefetch
Optimizes the system for applications that need high utilization of sequential memory access. This option is set to
Enabled
by default. You can disable this option for applications that need high utilization of random memory
access.
Hardware
Prefetcher
Enables or disables the hardware prefetcher. This option is set to
Enabled
by default.
DCU Streamer
Prefetcher
Enables or disables the Data Cache Unit (DCU) streamer prefetcher. This option is set to
Enabled
by default.
DCU IP Prefetcher
Enables or disables the Data Cache Unit (DCU) IP prefetcher. This option is set to
Enabled
by default.
Sub NUMA Cluster
Enables or disables the Sub NUMA Cluster. This option is set to
Disabled
by default.
Sub NUMA Cluster
Enables or disables the Sub NUMA Cluster. This option is set to
Disabled
by default.
UPI Prefetch
Enables you to get the memory read started early on DDR bus. The Ultra Path Interconnect (UPI) Rx path will
spawn the speculative memory read to Integrated Memory Controller (iMC) directly. This option is set to
Enabled
by default.
Logical Processor
Idling
Enables you to improve the energy efficiency of a system. It uses the operating system core parking algorithm and
parks some of the logical processors in the system which in turn allows the corresponding processor cores to
transition into a lower power idle state. This option can only be enabled if the operating system supports it. It is set
to
Disabled
by default.
x2APIC Mode
Enables or disables the x2APIC mode. This option is set to
Disabled
by default.
Dell Controlled
Turbo
Controls the turbo engagement. Enable this option only when
System Profile
is set to
Disabled
.
NOTE:
Depending on the number of installed processors, there might be up to four processor listings.
Number of Cores
per Processor
Controls the number of enabled cores in each processor. This option is set to
All
by default.
Processor Core
Speed
Specifies the maximum core frequency of the processor.
Pre-operating system management applications
51
Содержание PowerEdge R740
Страница 9: ...Figure 1 Supported configurations PowerEdge R740 system overview 9 ...
Страница 27: ...Figure 20 Jumper setting and memory information Figure 21 system task PowerEdge R740 system overview 27 ...
Страница 28: ...Figure 22 NVDIMM battery and mid tray hard drives 28 PowerEdge R740 system overview ...
Страница 141: ...Figure 94 Securing GPU 1 Installing and removing system components 141 ...
Страница 142: ...Figure 95 Installing GPU 2 and 3 142 Installing and removing system components ...