Davicom DM9000, Руководство пользователя

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DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
Final 17
Version: DM9000-DS-F02
June 26, 2002
6.13 EEPROM & PHY Address Register ( 0CH )
Bit Name Default Description
7:6 PHY_ADR 01,RW PHY Address bit 1 and 0, the PHY address bit [4:2] is force to 0. Force to 01 if
internal PHY is selected
5:0 EROA 0,RW EEPROM Word Address or PHY Register Address
6.14 EEPROM & PHY Data Register (EE_PHY_L
：
： ：
：
0DH EE_PHY_H
：
： ：
：
0EH)
Bit Name Default Description
7:0 EE_PHY_L X,RW EEPROM or PHY Low Byte Data
This data is made to write low byte of word address defined in Reg. CH to
EEPROM or PHY
7:0 EE_PHY_H X,RW EEPROM or PHY High Byte Data
This data is made to write high byte of word address defined in Reg. CH to
EEPROM or PHY
6.15 Wake Up Control Register ( 0FH )
Bit Name Type Description
7:6 RESERVED 0,RO Reserved
5 LINKEN 0,RW When set, it enables Link Status Change Wake up Event
This bit will not be affected after software reset
4 SAMPLEEN 0,RW When set, it enables Sample Frame Wake up Event
This bit will not be affected after software reset
3 MAGICEN 0,RW When set, it enables Magic Packet Wake up Event
This bit will not be affected after software reset
2 LINKST 0,RO When set, it indicates that Link Change and Link Status Change Event occurred
This bit will not be affected after software reset
1 SAMPLEST 0,RO When set, it indicates that the sample frame is received and Sample Frame Event
occurred. This bit will not be affected after software reset
0 MAGICST 0,RO When set, indicates the Magic Packet is received and Magic packet Event
occurred. This bit will not be affected after a software reset
6.16 Physical Address Register ( 10H~15H )
Bit Name Default Description
7:0 PAB5 X,RW Physical Address Byte 5 (15H)
7:0 PAB4 X,RW Physical Address Byte 4 (14H)
7:0 PAB3 X,RW Physical Address Byte 3 (13H)
7:0 PAB2 X,RW Physical Address Byte 2 (12H)
7:0 PAB1 X,RW Physical Address Byte 1 (11H)
7:0 PAB0 X,RW Physical Address Byte 0 (10H)