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http://www.google.com/search?q=test+one
http://www.google.com/search?q=test+zero
Notes:
It is possible to select a delay between write operation and succeeding verify of programmed
data (at condition the device is supplied) in intent to detect 'leak' of the bits.
Programmer hasn't capability to detect errors like too big current on the signal pins or such
"analog" errors
All tests are done at low frequency (meant compared with maximal speed of tested device),
therefore usage of such test is limited.
Conclusions:
The device programmer can provide only basic answer about health of the sRAM.
If you need test sRAM more deeply use please specialized sRAM tester.
Device / IC test
This command activates a test section for ICs, mainly Standard Logic IC. The ICs are sorted
by type of technology to groups/libraries.
First select an appropriate library, wished device and then a mode for test vectors run (LOOP,
SINGLE STEP). Control sequence and test results are displayed to Programmer activity log. In
case of need, it is possible to define the test vectors directly by user. Detailed description of
syntax and methods of creation testing vectors is described in example_e.lib file, which is in
programs installation folder.
Notes:
Testing of IC is done using test vectors at some (pretty low) speed. The tests by test vectors
can not detect all defects of the chip. Other words, if IC test report "FAIL", then device is
defective. But if is "PASS" reported, it means the chip passed our tests, but still might not
pass the tests, that check other - mainly dynamic - parameters of the tested IC.
Because the rising/falling edges of programmers are tuned for programming of chips, it may
happen the test of some chips fails, although the chips aren't defective (counters for
example).
Device / Jam/VME/SVF/STAPL/mDOC ... Player
Jam STAPL was created by Altera® engineers and is supported by a consortium of
programmable logic device (PLD) manufacturers, programming equipment makers, and test
equipment manufacturers.
The Jam™ Standard Test and Programming Language (STAPL), JEDEC standard JESD-71,
is a standard file format for ISP (In-System Programming) purposes. Jam STAPL is a freely
licensable open standard. It supports programming or configuration of programmable devices
and testing of electronic systems, using the IEEE 1149.1 Joint Test Action Group (JTAG)
interface. Device can be programmed or verified, but Jam STAPL does not generally allow
other functions such as reading a device.
The Jam STAPL programming solution consists of two components: Jam Composer and Jam
Player.
The Jam Composer is a program, generally written by a programmable logic vendor, that
generates a Jam file (.jam) containing the user data and programming algorithm required to
program a design into a device.