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Volt Digital) and Vd+3.3 (3.3V Digital) are created and made available to the I/O Modules via the 
Interconnect Port. The DSP Core voltage, Vd+1.2 is also created via a switching power supply. 

 
The dspstak 21262sx DSP Engine does not use Va+, Va+5 or Va-. These supplies are available to 

I/O Modules. If the I/O Module does not need a negative supply, you can power the dspstak 
21262sx with only a positive DC power supply. The recommended input voltages are 9 VAC or 9 to 

15VDC.  Since switching regulators are used for the digital supplies, the input voltage is not critical.  
 

In all cases, the DC supply or an unregulated DC supply created from an incoming AC supply 
should be less than 20VDC. This will protect both the DSP Engine and probably the components on 
the I/O Module. 

 
One final thing to remember: The nominal output voltage of a wall adapter is usually much lower 

than its actual output voltage. We recommend that unregulated DC wall adapters should have an 
maximum nominal voltage of 12VDC. 

 

RS-232 Interface 

 
The RS-232 interface is used to upload user application programs and to program the clock 
generator in the command mode. An application program may also use the RS-232 interface for its 

own purposes. The RS-232 port is provided by a dedicated microcontroller that also has other 
functions on the dspstak 21262sx. These functions are all available via the SPI port of the DSP.  The 

API for these functions is described in the Software Section of this manual. There are also software 
examples on calling these functions on the CD.   

 
The RS-232 interface is configured as a DCE (Data Communications Equipment) device. It uses a 

DB-9F connector that is designed to mate without crossover connections to the DB-9M connector 
found on PC compatible computers.  Connections are defined in the following table: 
 

Signal Direction Pin 

Notes 

 

 

 

 

DCD 

 

DCD, DTR & DSR are connected together 

RD 

DCE -> DTE 

 

TD 

DTE -> DCE 

 

DTR 

 

DCD, DTR & DSR are connected together 

SIGNAL GND 

 

 

DSR 

 

DCD, DTR & DSR are connected together 

RTS 

DTE -> DCE 

Not currently supported 

CTS 

DCE -> DTE 

Not currently supported 

RI  

NC 

  

 
 
dspstak™ 21262sx User Manual 

 

Page 8 

 

Содержание dspstak 21262sx

Страница 1: ...Danville Signal Processing Inc dspstak 21262sx User Manual Version 1 10...

Страница 2: ...ice Updated operating manuals and product specification sheets are available at our website for downloading This manual may contain errors omissions or typo s Please send your comments suggestions and...

Страница 3: ...mulation Port 10 dspstak 21262sx Architecture 10 Hardware ADSP 21262 Core 10 DAI 10 Parallel Port 13 SPI Port 14 Programming the dspstak 21262sx 15 Programming Modes 15 Configuration Jumpers 16 Progra...

Страница 4: ...Addressing USB PLD Registers 29 PLD Output USB Status Registers 29 Memory Map 30 USB Port 30 PLD Output Registers 32 Software 34 Schematic 34 Mechanical Drawings 34 Product Warranty 35 dspstak 21262s...

Страница 5: ...I O such as RS 232 and USB We currently have products based on Analog Devices SHARC processors The I O Modules may include signal conditioning electronics A D and or D A data converters audio transcei...

Страница 6: ...es very flexible peripherals including six independent serial ports SPORTs and a SPI port The dspstak 21262sx Interconnect Port supports the complete DAI interface SPI general I O clocks and power con...

Страница 7: ...can assume that future dspstak DSP Engines based on the 3rd generation SHARC family will support the Interconnect Port in a manner similar to the dspstak 21262sx Power Supply The dspstak 21262sx uses...

Страница 8: ...maximum nominal voltage of 12VDC RS 232 Interface The RS 232 interface is used to upload user application programs and to program the clock generator in the command mode An application program may al...

Страница 9: ...n the Interconnect Port The three programmable clocks on the Interconnect Port allow I O Modules to use convenient clocks for whatever devices that might be present For example an ADC might use an 18...

Страница 10: ...eart of the dspstak 21262sx is an Analog Devices ADSP 21262 DSP This manual does not discuss the internal workings of this DSP the assembly language and other details specific to this DSP You should r...

Страница 11: ...tal Ground Main Return 9 LED0 PLD 3 3V Digital Output 9 LED1 PLD 3 3V Digital Output 10 LED2 PLD 3 3V Digital Output 10 LED3 PLD 3 3V Digital Output 11 LED4 PLD 3 3V Digital Output 11 IO5 SPISS1 DAI 2...

Страница 12: ...e Clock 28 RFS1 DAI 15 28 TFS1 DAI 16 29 RCLK1 DAI 17 29 TCLK1 DAI 18 30 RESET1 PLD 30 GND 31 DTB1 DAI 19 31 DRB1 DAI 20 32 GND 32 Vd 3 3 LEDs IO5 7 SPI_SSs DAI 1 3 Enable Resets are controlled by the...

Страница 13: ...an be used to connect from a dspstak I O Module to JH2 but there is no guarantee that another dspstak DSP Engine will be compatible Samtec is a supplier for this type of connector JH2 Pinout Pin Name...

Страница 14: ...tion and user EE memory It communicates over the SPI port using Flag 2 as its slave select Refer to the Peripheral Microcontroller API section of this manual for more information The SPI Port is also...

Страница 15: ...programming modes are reserved for standard dspstak 21262sx functions and the remaining four are available for user programs For example you could use Mode 0 as a means to bootload one version of your...

Страница 16: ...ntroller the ADSP 21262 and the Interconnect Port The Interconnect Port clocks are SYSCLK MCLK0 MCLK1 The CY22393 has three independent PLLs that allow you to generate clocks that are appropriate for...

Страница 17: ...Here are the basic steps to reprogramming the CY22393 Configure the dspstak 21262sx to operate in Mode 7 M2 M1 M0 Jumpers Off Connect to an ASCII Terminal Program via RS 232 A 9 pin to 9 pin cable wit...

Страница 18: ...It is still there and it loads your program but it does so silently You write your DSP applications as normal and create a ldr file Boot Type SPI Slave Format Binary Width 8 You don t really need to...

Страница 19: ...boot process This will bring a new DSP prompt signifying Command Mode Type to view a list of available commands Type U to upload a new program file Your program must be a ldr ADI loader file with the...

Страница 20: ...culated Type Q to quit Command Mode and the application program will boot There are a number of additional commands that are available in Command Mode For example you can read write and erase EE memor...

Страница 21: ...and Summary Name Description PM_Cmd_NOP 0x00 No Operation PM_Cmd_COM_WR 0x01 Transmit a byte from the RS 232 port PM_Cmd_COM_RD 0x02 Receive a byte from the RS 232 port PM_Cmd_VERSION 0x03 Firmware ve...

Страница 22: ...nless you are doing commands regularly it s best to always do a PM_Cmd_NOP before you read the status bits Status Bits Bit 0 UART RX Data Available Bit 1 UART TX Space Available Bit 2 Reserved Bit 3 R...

Страница 23: ...ctive the application must ping the WD input of the Peripheral Microcontroller with a state change before the watchdog timer expires or the system will reboot The watchdog timer is initially disabled...

Страница 24: ...ur program to execute different applications depending on the Mode settings For example your product might be an encoder in Mode 0 and a decoder in Mode 1 You would only need to upload one program for...

Страница 25: ...y bytes at the selected baud rate You should check the UART TX Space Available Status bit in the next packet If the last byte was unsuccessfully added to the FIFO the Transmit FIFO was full the applic...

Страница 26: ...sponse 0x00 This command resets the UART flushes the Transmit and Receive FIFOs and clears the UART Overrun Status bit PM_Cmd_COM_RTS_CTS Description RS 232 Handshaking Command 0x0C Data Bit 0 is CTS...

Страница 27: ...hould disable writes after you are done writing the EE Memory EE_WREN is always disabled after a system reset PM_Cmd_EE_WR Description Write EE at current EE Address Command 0x06 Data EE Data Response...

Страница 28: ...s Command 0x0D Data Don t Care Response EE Data EE Data is read from the current address pointed to by the EE Address Pointer This address is set by the EE_ADDR command and auto incremented after ever...

Страница 29: ...H2 for external Parallel Port expansion as long as your devices are mapped into the lower half of the memory In other words AD15 must be demultiplex as either A15 or A23 0 The PLD and USB require that...

Страница 30: ...rivers on our distribution CD The driver files includes dspstak inf files that are used for installation in Microsoft Windows operating systems If you are using another OS you may want to compare the...

Страница 31: ...byte is available So here s the trick We address the Parallel Port to read from Address 0x8FFE You may recall that only the upper nibble is decoded by the PLD The address then auto increments to 0x900...

Страница 32: ...ect lines If the pin is configured as GP I O the DAI connects to the pin as follows IO7 DAI_P1 IO6 DAI_P3 IO5 DAI_P2 PLD_OUT0 Description 3 3V Digital Output Destination Interconnect Port Address 0xB0...

Страница 33: ...1 Active SPISS_MASK D12 1 Active All other bits are Don t Care This register is used for SPI slave select expansion If the mask bit is set the pin will follow the state of FLAG3 on the ADSP 21262 The...

Страница 34: ...our customers through our web site Send an email to support danvillesignal com to gain access to the customer section of our web site Schematic The Distribution CD includes a schematic diagram of the...

Страница 35: ...nal Processing shall at its option either repair or replace software media or firmware which do not execute their programming instructions due to such defects Danville Signal Processing does not warra...

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