Clock reprogramming is managed entirely by the Peripheral Microcontroller via its RS-232 port. It is
not dependent on the ADSP-21262 DSP. The Peripheral Microcontroller also gets its clock from
the CY22393 so steps have been taken to protect this clock from inadvertent modification. The
following table describes the CY22393 mapping to the dspstak 21262sx.
Clock Configuration – CY22393
Clock CY22393
Default
Notes
Peripheral Microcontroller XBUF
18.432 MHz
Xtal, Always On
DSP Clock
CLKB
24.576 MHz
JH1 Pins 2&3 shorted
SYSCLK
CLKC
24.576 MHz
Interconnect Port
MCLK0
CLKD
12.288 MHz
Interconnect Port – SPORT 0
MCLK1
CLKA
12.288 MHz
Interconnect Port – SPORT 1
JH1-5 CLKE
Off
Not
used
It is also possible to provide an external clock to the ADSP-21262 via the Interconnect Port. In this
configuration, JH1 Pins 1&2 are shorted. It might be prudent to disable the DSP Clock (CLKB) in this
situation.
Here are the basic steps to reprogramming the CY22393:
•
Configure the dspstak 21262sx to operate in Mode 7 (M2,M1,M0 – Jumpers Off).
•
Connect to an ASCII Terminal Program via RS-232. A 9 pin to 9 pin cable with no twists is
appropriate on PC compatible computers. The Serial Configuration must be 19.2K, 8, 1, N.
Handshaking lines are ignored. A free terminal program is provided on the distribution CD.
•
Create a new JEDEC file using CyberClocks™. The file 21262.JED is included on the CD.
This is the factory default and a good place to start.
•
Power Up or Reset the dspstak 21262sx. You should see a
Clock>
prompt. You may wish to
type
?
to see the available commands.
•
Type
U
to upload a new JEDEC file. This will copy the file into the Working Registers (RAM).
You can also use the
L
command to reload the factory default settings.
•
If you are sure that you are ready to write, type the
W
command. You can verify your results
against the Working Registers by typing
V.
•
Exit the Clock Mode with the
Q
command. This will vector you to Mode 6 where you can
upload application programs.
dspstak™ 21262sx User Manual
Page 17
