Configuration Jumpers
JH5 is also used to select the boot configuration and clock configuration of the ADSP-21262. The
connections are made directly to the ADSP-21262 BOOTCFG1-0 & CLKCFG1-0 Pins. In most
cases, the factory default settings will not need to be changed.
Boot Configuration – Jumpers (JH5)
Boot Cfg
Name
B1 B0
00
SPI Slave Boot
On On
01
SPI Master Boot
On Off Default
10
Parallel Port Boot
Off On
11 Internal
Boot
Off Off
* Jumper On = 0
Clock Configuration – Jumpers (JH5)
Mode Name
CF1 CF0
00 3:1
Core/ClkIn
On On
01 16:1
Core/ClkIn
On Off
10 8:1
Core/ClkIn
Off On Default
11 Undefined
Off Off
* Jumper On = 0
Programming the Clock – Mode 7
The dspstak 21262sx uses a Cypress Semiconductor CY22393 programmable clock generator to
provide clocks for the Peripheral Microcontroller, the ADSP-21262, and the Interconnect Port.
The Interconnect Port clocks are SYSCLK, MCLK0 & MCLK1.
The CY22393 has three independent PLLs that allow you to generate clocks that are appropriate for
your situation. By using the default DSP Clock setting - 24.576 MHz, the DSP will operate with a
Core Clock of 196.6 MHz (JH5 set to default). The three programmable clocks on the Interconnect
Port allow I/O Modules to use convenient clocks for whatever devices that might be present. For
example, an ADC might use a 18.432 MHz MCLK to sample at 96k or a 19.6608 MHz MCLK to
sample at 102.4k.
If you want to reprogram the CY22393, you should review the CY22393 data sheet. You will also
need the Cypress program, CyberClocks™ to generate a JEDEC file of clock parameters. The data
sheet and the program are available on the Cypress web site and there are links on the Danville
web site at
http://www.danvillesignal.com/index.php?id=dspdev_links
.
dspstak™ 21262sx User Manual
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