PLD Output Registers
PLD_DAI_SPI_SELECT
Description: Selects I/O or SPI SS mapping
Destination: Interconnect Port
Address: 0xA000
IO7/#SPISS3:
D15
0 – IO7
1 – #SPISS3
IO6/#SPISS2:
D14
0 – IO6
1 – #SPISS2
IO5/#SPISS1:
D13
0 – IO5
1 – #SPISS1
All other bits are Don’t Care.
This register determines whether the IO Pins on the Interconnect Port are bi-
directional GP I/O Pins or SPI slave select lines. If the pin is configured as GP I/O, the
DAI connects to the pin as follows:
IO7 = DAI_P1
IO6 = DAI_P3
IO5 = DAI_P2
PLD_OUT0
Description: 3.3V Digital Output
Destination: Interconnect Port
Address: 0xB000
LED3:
D15
0
–
Output
Low
LED2:
D14
0
–
Output
Low
LED1:
D13
0
–
Output
Low
LED0:
D12
0
–
Output
Low
All other bits are Don’t Care.
This register causes the LED3-LED0 lines on the Interconnect Port to be driven.
Although these pins refer to LEDs, they can be used to drive other devices. There are
no series limiting resistors in these lines.
dspstak™ 21262sx User Manual
Page 32
