PLD_OUT1
Description: 3.3V Digital Output
Destination: Interconnect Port
Address: 0xC000
#RESET:
D15
0 – Output Low
#RESET1
D14
0 – Output Low
#RESET0:
D13
0 – Output Low
LED4:
D12
0
–
Output
Low
All other bits are Don’t Care.
This register causes the LED4 and the RESET lines on the Interconnect Port to be
driven. There are no series limiting resistors in these lines.
PLD_SPI_SELECT
Description: 3.3V Digital Output
Destination: Internal Mask
Address: 0xD000
SPISS3_MASK:
D15
1 – Active
SPISS2_MASK:
D14
1 – Active
SPISS1_MASK:
D13
1 – Active
SPISS_MASK:
D12
1
–
Active
All other bits are Don’t Care.
This register is used for SPI slave select expansion. If the mask bit is set, the pin will
follow the state of FLAG3 on the ADSP-21262. The corresponding
PLD_DAI_SPI_SELECT bit must also be set. SPISS_MASK does not have an alternate
function.
Example:
Write 0x0000A000 with PLD_SPI_SELECT previously set to
0x0000F000.
This will cause #SPISS3 and #SPISS1 to follow FLAG3.
In most cases, only one mask bit will be set. This will allow only one device to be
selected during a SPI transfer. This is required for bi-directional devices where more
than one active slave select will cause bus contention on the SPI SO line.
dspstak™ 21262sx User Manual
Page 33
