DS87C550 High-Speed Microcontroller User’s Guide Supplement
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writing a “1” to the STRT/BSY bit of the ADCON1 register, or alternately by a falling edge on the
STADC pin when the ADEX bit of the ADCON1 is set. When the conversion starts, the analog value on
the selected pin is held in the sample and hold circuitry for the remainder of the conversion.
The “latched” analog signal is applied to the input of the 10-bit successive approximation converter. The
converter requires 16-clock cycles (provided from the prescaler) to perform a conversion. Due to the
dynamic nature of the conversion process, the clock into the converter (t
ACLK
) must be in the range of 1.0
µ
s
≤≤≤≤
t
ACLK
≤≤≤≤
6.25
µ
s. Therefore the fastest possible conversion requires 16.0
µ
s, and the slowest
conversion requires 100
µ
s. During the conversion process, the STRT/BSY (ADCON1.7) bit remains
high until the conversion is complete at which time the hardware resets it. The hardware also sets the
EOC bit (ADCON1.6) when the conversion is complete, and software must clear it if it is to be used on
the next conversion.
After the first conversion is complete, another can be initiated using the STRT/BSY bit as described.
Alternately, another conversion will be started automatically at the end of the first conversion if the
CONT/SS bit (ADCON1.5) is set. In this continuous conversion mode, it is probably most convenient to
enable the A/D interrupt function otherwise continuous polling (and clearing) the EOC bit would be
required.
At the end of a conversion, the result is latched into a 10-bit latch, and is made available to the two A/D
result registers ADMSB and ADLSB. As discussed above, the result may be presented in either 10-bit
mode or 8-bit mode as selected by the user. Further details of the A/D functions are discussed below.
PRESCALER
The A/D clock Prescaler allows a wide selection of clock frequencies to be used for the conversion
process. It divides the machine cycle clock frequency by the value written to the APS3:0 bits
(ADCON1.3:0), and provides this resulting clock to the successive approximation converter. Since the
machine cycle clock can be osc/1, osc/2, ocs/4, or osc/1024 as determined by bits CD1:0 and 4X/ X
2
of
the PMR register, then the period of the clock output from the prescaler is given in Table AD1.
A/D Conversion Clock Period Calculation :
Table A/D1
4X/
X
2
CD1:0
t
ACLK
1
00
(t
OSC
*1)*(APS3:0+1)
0
00
(t
OSC
*2)*(APS3:0+1)
X
01
(t
OSC
*4)*(APS3:0+1)
X
10
(t
OSC
*4)*(APS3:0+1)
X
11
(t
OSC
*1024)*(APS3:0+1)
As an brief example of this calculation, assume that the processor is running using a 33.0 MHz crystal,
and is in its reset default condition for the machine clock. If it is desired to set the A/D for its fastest
possible conversion time (recalling that 1.0
µ
s
≤≤≤≤
t
ACLK
≤≤≤≤
6.25
µ
s), to what value what should APS3:0 be
set. From row 3 of Table A/D1, it can be seen that 8 is the desired value.
(1/33Mhz * 4) * (8+1) = 1.091
µ
s
As a further example, if the clock multiplier is used in 2X mode along with an 11.0592 MHz crystal , then
from row two of the table it can be shown that 5 is the desired value.
