Cypress Traveo S6J32E Series, Руководство пользователя

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Document Number: 002-10689 Rev *H Page 107 of 166
S6J32E, S6J32F, S6J32G Series
8.4.7.4 I
2
C Timing (SMR:MD2-0=0b100)
(Condition: See 8.2. Operation Assurance )
Parameter Symbol Pin Name Conditions
Standard
Mode
Fast Mode
Unit Remarks
Min Max Min Max
SCL clock frequency
f
SCL
SCL4, 10, 12,
16, and 17
(CL = 50 pF,
I
OL
= -2 mA,
I
OH
= 2 mA),
(CL = 20 pF,
I
OL
= -1 mA,
I
OH
= 1 mA)
0 100 0 400 kHz
Repeat "start"
condition hold time
SDA
↓ →
SCL
↓
t
HDSTA
SDA4, 10, 12,
16, and 17
SCL4, 10, 12,
16, and 17
4.0 - 0.6 - µs
Period of "L" for
SCL clock
t
LOW
SCL4, 10, 12,
16, and 17
4.7 - 1.3 - µs
Period of "H" for
SCL clock
t
HIGH
SCL4, 10, 12,
16, and 17
4.0 - 0.6 - µs
Repeat "start"
condition setup time
SCL
↑ →
SDA
↓
t
SUSTA
SDA4, 10, 12,
16, and 17
SCL4, 10, 12,
16, and 17
4.7 - 0.6 - µs
Data hold time
SCL
↓ →
SDA
↓ ↑
t
HDDAT
SDA4, 10, 12,
16, and 17
SCL4, 10, 12,
16, and 17
0 3.45
*1
0 0.9
*2
µs
Data setup time
SDA
↓ ↑ →
SCL
↑
t
SUDAT
SDA4, 10, 12,
16, and 17
SCL4, 10, 12,
16, and 17
250 - 100 - ns
"Stop" condition setup
time
SCL
↑ →
SDA
↑
t
SUSTO
SDA4, 10, 12,
16, and 17
SCL4, 10, 12,
16 and 17
4.0 - 0.6 - µs
Bus-free time between
"stop" condition and
"start" condition
t
BUF
- 4.7 - 1.3 - µs
Noise filter
t
SP
-
2t
CLK_
COMP
-
2t
CLK_
COMP
- ns
Notes:
−
*1: The maximum t
HDDAT
only has to be met if the device does not extend the "L" width (t
LOW
) of the
SCL signal.
−
*2: A fast mode I
2
C bus device can be used on a standard mode I
2
C bus system as long as
the device satisfies the requirement of "t
SUDAT
≥ 250 ns".
−
SCL4, 10, 12 and SDA4, 10, 12 only support the standard mode.