FM33256B
Document Number: 001-86213 Rev. *C
Page 5 of 39
Overview
The FM33256B device combines a serial nonvolatile RAM with
a real time clock (RTC) and a processor companion. The
companion is a highly integrated peripheral including a
processor supervisor, analog comparator, a nonvolatile counter,
and a serial number. The FM33256B integrates these
complementary but distinct functions under a common interface
in a single package. The product is organized as two logical
devices. The first is a memory and the second is the companion
which includes all the remaining functions. From the system
perspective they appear to be two separate devices with unique
opcodes on the serial bus.
The memory is organized as a standalone nonvolatile SPI
memory using standard opcodes. The real time clock and
supervisor functions are accessed under their own opcodes. The
clock and supervisor functions are controlled by 30 special
function registers. The RTC alarm and some control registers are
maintained by the power source on the V
BAK
pin, allowing them
to operate from battery or backup capacitor power when V
DD
drops below a set threshold. Each functional block is described
below.
Memory Architecture
The FM33256B is available with 256-Kbit of memory. The device
uses two-byte addressing for the memory portion of the chip.
This makes the device software compatible with its standalone
memory counterparts, such as the FM25W256.
The memory array is logically organized as 32,768 × 8 bits and
is accessed using an industry-standard serial peripheral
interface (SPI) bus. The memory is based on F-RAM technology.
Therefore it can be treated as RAM and is read or written at the
speed of the SPI bus with no delays for write operations. It also
offers effectively unlimited write endurance unlike other
nonvolatile memory technologies. The SPI protocol is described
on
page 23
.
The memory array can be write-protected by software. Two bits
(BP1, BP0) in the Status Register control the protection setting.
Based on the setting, the protected addresses cannot be written.
The Status Register & Write Protection is described in more
detail on
page 26
.
Processor Companion
In addition to nonvolatile RAM, the FM33256B incorporates a
real time clock with alarm and highly integrated processor
companion. The companion includes a low-V
DD
reset, a
programmable watchdog timer, a 16-bit nonvolatile event
counter, a comparator for early power-fail detection or other
purposes, and a 64-bit serial number.
Processor Supervisor
Supervisors provide a host processor two basic functions:
Detection of power supply fault conditions and a watchdog timer
to escape a software lockup condition. The FM33256B has a
reset pin (RST) to drive a processor reset input during power
faults, power-up, and software lockups. It is an open drain output
with a weak internal pull-up to V
DD
. This allows other reset
sources to be wire-OR'd to the RST pin. When V
DD
is above the
programmed trip point, RST output is pulled weakly to V
DD
. If
V
DD
drops below the reset trip point voltage level (V
TP
), the RST
pin will be driven LOW. It will remain LOW until V
DD
falls too low
for circuit operation which is the V
RST
level. When V
DD
rises
again above V
TP
, RST continues to drive LOW for at least 30 ms
(t
RPU
) to ensure a robust system reset at a reliable V
DD
level.
After t
RPU
has been met, the RST pin will return to the weak
HIGH state. While RST is asserted, serial bus activity is locked
out even if a transaction occurred as V
DD
dropped below V
TP
. A
memory operation started while V
DD
is above V
TP
will be
completed internally.
Table 1
below shows how bits VTP(1:0) control the trip point of
the low-V
DD
reset. They are located in register 18h, bits 1 and 0.
The reset pin will drive LOW when V
DD
is below the selected V
TP
voltage, and the SPI interface and F-RAM array will be locked
out.
Figure 2
illustrates the reset operation in response to a low
V
DD
.
A watchdog timer can also be used to drive an active reset signal.
The watchdog is a free-running programmable timer. The
timeout period can be software programmed from 60 ms to 1.8
seconds in 60 ms increments via a 5-bit nonvolatile setting
(register 0Ch).
Table 1. VTP setting
VTP Setting
VTP1
VTP0
2.6 V
0
0
2.75 V
0
1
2.9 V
1
0
3.0 V
1
1
Figure 2. Low V
DD
Reset
Figure 3. Watchdog Timer
V
DD
V
TP
t
RPU
RST
Timebase
Down Counter
Watchdog
Timer Settings
100 ms
clock
WDE
RST
WR(3:0)
= 1010b to restart
