FM33256B
Document Number: 001-86213 Rev. *C
Page 25 of 39
Power Up to First Access
The FM33256B is not accessible for a t
PU
time after power-up.
Users must comply with the timing parameter, t
PU
, which is the
minimum time from V
DD
(min) to the first CS LOW.
Command Structure
There are eight commands, called opcodes, that can be issued
by the bus master to the FM33256B. They are listed in
Table 1
.
These opcodes control the functions performed by the memory
and processor companion.
WREN - Set Write Enable Latch
The FM33256B will power up with writes disabled. The WREN
command must be issued before any write operation. Sending
the WREN opcode allows the user to issue subsequent opcodes
for write operations. These include writing the Status Register
(WRSR) and writing the memory (WRITE).
Sending the WREN opcode causes the internal Write Enable
Latch to be set. A flag bit in the Status Register, called WEL,
indicates the state of the latch. WEL = ’1’ indicates that writes are
permitted. Attempting to write the WEL bit in the Status Register
has no effect on the state of this bit – only the WREN opcode can
set this bit. The WEL bit will be automatically cleared on the rising
edge of CS following a WRDI, a WRSR, a WRPC or a WRITE
operation. This prevents further writes to the Status Register or
the F-RAM array without another WREN command.
Figure 17
illustrates the WREN command bus configuration.
WRDI - Reset Write Enable Latch
The WRDI command disables all write activity by clearing the
Write Enable Latch. The user can verify that writes are disabled
by reading the WEL bit in the Status Register and verifying that
WEL is equal to ‘0’.
Figure 18
illustrates the WRDI command bus
configuration.
Table 8. Opcode Commands
Name
Description
Opcode
WREN
Set write enable latch
0000 0110b
WRDI
Reset write enable latch
0000 0100b
RDSR
Read Status Register
0000 0101b
WRSR
Write Status Register
0000 0001b
READ
Read memory data
0000 0011b
WRITE
Write memory data
0000 0010b
RDPC
Read Processor Companion
0001 0011b
WRPC
Write Processor Companion
0001 0010b
Figure 17. WREN Bus Configuration
Figure 18. WRDI Bus Configuration
0 0 0 0 0 1 1 0
CS
SCK
SI
SO
HI-Z
0 1 2 3 4 5 6 7
0 0 0
CS
SCK
SI
SO
HI-Z
0 1 2 3 4 5 6 7
0
0
0
0
1
