FM33256B
Document Number: 001-86213 Rev. *C
Page 24 of 39
Status Register
The FM33256B has an 8-bit Status Register. The bits in the
Status Register are used to configure the device. These bits are
described in
Table 10 on page 26
.
SPI Modes
The FM33256B may be driven by a microcontroller with its SPI
peripheral running in either of the following two modes:
■
SPI Mode 0 (CPOL = 0, CPHA = 0)
■
SPI Mode 3 (CPOL = 1, CPHA = 1)
For both these modes, the input data is latched in on the rising
edge of SCK starting from the first rising edge after CS goes
active. If the clock starts from a HIGH state (in mode 3), the first
rising edge after the clock toggles is considered. The output data
is available on the falling edge of SCK.
The two SPI modes are shown in
Figure 15 on page 24
and
Figure 16 on page 24
. The status of the clock when the bus
master is not transferring data is:
■
SCK remains at 0 for Mode 0
■
SCK remains at 1 for Mode 3
The device detects the SPI mode from the status of the SCK pin
when the device is selected by bringing the CS pin LOW. If the
SCK pin is LOW when the device is selected, SPI Mode 0 is
assumed and if the SCK pin is HIGH, it works in SPI Mode 3.
Figure 13. System Configuration with SPI Port
C S 1
C S 2
FM33256B
FM33256B
SCK
SI
SO
SCK
SI
SO
CS
CS
SCK
MOSI
MISO
SPI
Microcontroller
Figure 14. System Configuration without SPI Port
FM33256B
Microcontroller
SCK
SI
SO
CS
P1.2
P1.1
P1.0
Figure 15. SPI Mode 0
Figure 16. SPI Mode 3
LSB
MSB
7
6
5
4
3
2
1
0
CS
SCK
SI
0
1
2
3
4
5
6
7
CS
SCK
SI
7
6
5
4
3
2
1
0
LSB
MSB
0
1
2
3
4
5
6
7
