FM33256B
Document Number: 001-86213 Rev. *C
Page 18 of 39
0Ch
Watchdog Control
D7
D6
D5
D4
D3
D2
D1
D0
WDE
-
-
WDET4
WDET3
WDET2
WDET1
WDET0
WDE
Watchdog Enable: When WDE = ‘1’, a watchdog timer fault will cause the RST signal to go active. When WDE =
‘0’ the timer runs but has no effect on the RST pin. Nonvolatile, read/write.
WDET(4:0)
Watchdog EndTime: Sets the ending time for the watchdog window timer with 60 ms (min.) resolution. The window
timer allows independent leading and trailing edges (start and end of window) to be set. New watchdog timeouts are
loaded when the timer is restarted by writing the 1010b pattern to WR(3:0). To save power (disable timer circuit), the
EndTime may be set to all zeroes. Nonvolatile, read/write.
Watchdog EndTime
WDET4
WDET3
WDET2
WDET1
WDET0
Disables Timer
0
0
0
0
0
(min.)
(max.)
60 ms
200 ms
0
0
0
0
1
120 ms
400 ms
0
0
0
1
0
180 ms
600 ms
0
0
0
1
1
.
.
.
.
1200 ms
4000 ms
1
0
1
0
0
1260 ms
4200 ms
1
0
1
0
1
1320 ms
4400 ms
1
0
1
1
0
.
.
.
.
1740 ms
5800 ms
1
1
1
0
1
1800 ms
6000 ms
1
1
1
1
0
1860 ms
6200 ms
1
1
1
1
1
Table 7. Register Description
(continued)
Address
Description