Hardware
CY4502 EZ-
PD™ CCG2 Development Kit Guide, Doc. No. 001-96601 Rev. *G
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Table 4-1. USB Type-C Plug Signals
Signal Group
Signal
Description
USB 3.1
SSTXp1, SSTXn1
SSRXp1, SSRXn1
SSTXp2, SSTXn2
SSRXp2, SSRXn2
The SuperSpeed USB serial data interface defines one differential transmit pair and one
differential receive pair.
On a USB Type-C plug and receptacle, two sets of SuperSpeed USB signal pins are defined to
enable the plug flipping feature.
USB 2.0
Dp, Dn
The USB 2.0 serial data interface defines a differential pair. On a USB Type-C receptacle, two
sets of USB 2.0 signal pins are defined to enable the plug flipping feature.
Configuration
CC
CC channel in the plug used for connection detect and interface configuration
Auxiliary signals
SBU1, SBU2
Sideband use
Power
VBUS
USB cable bus power
VCONN
Type-C cable plug power
GND
USB cable return current path
Note:
Four capacitors are needed on the VBUS pins of the Type-C connector according to the
. A 10-nF bypass capacitor (minimum voltage rating of 30 V) is required for the VBUS pin in the full-featured
cable at each end of the cable. The bypass capacitors should be placed as close as possible to the VBUS pins of the
Type-C connector.
In the CY4502 board, the capacitors on the VBUS pins are not mounted as the parasitic capacitance itself sums up to
> 10 nF.
4.4 SWD Connector
The CY4502 board contains two SWD connectors for programming: J3 and J4.
The SWD connectors are used to program and debug the CCG2 devices. SWD_CLK is the clock coming from the master
(programmer) and SWD_IO is the bidirectional data bus used to transmit or receive data from the CCG2 device, as shown
in
. The RESET signal is used to pull down the RESET pin of the CCG2 device to bring it into the Programming
mode.
Figure 4-6. SWD Connectors for Programming
