Cypress EZ-PD CCG2 Development Kit, Руководство пользователя

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Kit Operation
CY4502 EZ-
PD™ CCG2 Development Kit Guide, Doc. No. 001-96601 Rev. *G
14
Function Jumper Purpose Default
SOP”
response selection
for U1
J8
Jumpers to enable SOP” response for U1 (CYPD2103-20FNXIT):
Short: Enables SO
P” response by pulling GPIO (D3) low. The CYPD2103 firmware
is configured to detect the presence of the VCONN supply in the VCONN1/VCONN2
pins for determining the responsiveness to SOP packets. The CCG2 device
powered through VCONN1 considers itself to be the host end of the cable (that is,
connected to the DFP) and thus responds to SOP’. CCG2 powered through
VCONN2 considers itself to be the device end of the cable (that is, connected to the
UFP) and thus responds to SOP”. For the two-chip EMCA solution, with both CCG2
controllers powered as shown in
Figure 3-9 , the GPIO (pin D3) must be pulled low.
Open: Disables SOP” response. CCG2 responds to SOP’ packets only. For the
single-chip EMCA solution, shown in
Figure 3-5 , the GPIO (pin D3) must be left
floating. When the GPIO (pin D3) is left floating, the CYPD2103 firmware is
configured to always respond only to SOP’ packets.
Note: According to
the USB PD specification, SOP’ packets are recognized by the
cable controller in one of the cable plugs attached to the DFP and are not
recognized by the UFP or the other cable plug. Similarly, SOP’’ packets are
recognized by the cable controller in one of the cable plugs attached to the UFP and
are not recognized by the UFP or the other cable plug.
Open
SOP”
response selection
for U2
J13 Jumpers to enable SOP
” response of U2 (CYPD2103-14LHXIT):
Short: E
nables SOP” response by pulling GPIO (D3) low. The CYPD2103 firmware
is configured to detect the presence of the VCONN supply in the VCONN1/VCONN2
pins for determining the responsiveness to SOP packets. The CCG2 device
powered through VCONN1 considers itself to be the host end of the cable (that is,
connected to the DFP) and thus responds t
o SOP’. CCG2 powered through
VCONN2 considers itself to be the device end of the cable (that is, connected to the
UFP) and
thus responds to SOP”. For the two-chip EMCA solution, with both CCG2
controllers powered as shown in Figure 3-9 , the GPIO (pin D3) must be pulled low.
Open: D
isables SOP” response. CCG2 responds only to SOP’ packets. For the
single-chip EMCA solution shown in Figure 3-5 , the GPIO (pin D3) must be left
floating. When the GPIO (pin D3) is left floating, the CYPD2103 firmware is
configured to always respond only
to SOP’ packets.
Note: According to
the USB PD specification, SOP’ packets are recognized by the
cable controller in one of the cable plugs attached to the DFP and are not
recognized by the UFP or the other cable plug. Similarly, SOP’’ packets are
recognized by the cable controller in one of the cable plugs attached to the UFP and
are not recognized by the UFP or the other cable plug.
Open
3.3 CCG2 Single-Chip EMCA Application
The CY4502 board can operate in a single-chip EMCA application, as shown in Figure 3-5 . Follow these steps to configure
the board for this mode (depicted in Figure 3-4 ):
1. Short pins 1 and 2 of jumper J6.
2. Short pins 2 and 3 of jumper J7.
3. Leave jumpers J8 and J13 open.
4. Leave jumper J5 open.
Follow instructions in section 3.7 to test the CY4502 board.