Getting Started with EZ-
PD™ CCG3
Document No. 002-00210 Rev. *A
9
Figure 5
.
CCG3 Firmware Architecture Diagram
CC
Application Layer
CCG3 Hardware
Hardware Abstraction Layer
Flash
SCB
GPIO
Timer
Type-C &
PD
Port
Management
Alternate
Modes
Host
Processor I/f
Low Power
(Sleep)
Solution Management Layer
Embedded Controller
(EC)
Type-C
Connector
CCG3 Bootloader
I
2
C
External HW Control
(FET, Mux, etc)
Solution Specific Tasks
Firmware
Hardware
Type-C & USB-PD Stack
3.2
Flash Memory Organization
The CCG3 device has 128 KB of flash divided into two banks of 64 KB each, which allows support for dual firmware
images. Dual firmware images enable firmware updates to be fail-safe; that is, the firmware update does not interrupt
the normal operation of the device. All applications supported by CCG3 support dual firmware images.
shows the flash map of the CCG3 device.
Figure 6
.
CCG3 Firmware Organization
