Getting Started with EZ-
PD™ CCG3
Document No. 002-00210 Rev. *A
8
3.1
CCG3 Firmware Architecture Overview
shows a block diagram of the CCG3 firmware architecture. The CCG3 firmware architecture allows users to
implement a variety of USB-PD applications using the CCG3 device. It contains the following components:
Hardware Abstraction Layer (HAL):
This includes the low-level drivers for various hardware blocks of the
CCG3 device. This includes drivers for the Type-C and USB-PD block, Serial Communication Blocks (SCBs),
GPIOs, flash module, and timer module.
USB Type-C and USB-PD Protocol Stack:
This is the complete USB-PD protocol stack that includes the Type-
C and USB-PD port managers, USB-PD protocol layer, the USB-PD policy engine, and the device policy
manager. The device policy manager is designed to allow all policy decisions to be made at the application level,
either on an external Embedded Controller (EC) or in the CCG3 firmware itself.
Application Layer:
This is the layer responsible for managing the functions of the PD port, handling alternate
modes, power management, and also manages the Host Processor Interface (HPI). It is further sub-categorized
into the following components:
o
Port Management:
This module handles all of the PD port management functions including the algorithm
for optimal contract negotiations, source and sink power control, source voltage selection, port role
assignment, and swap request handling.
o
Alternate Modes:
This module implements the alternate mode handling for CCG as a DFP and UFP. A fully
tested implementation of the DisplayPort alternate mode with CCG as the DFP is p
r
ovided. The module also
allows users to implement their own alternate mode support in both DFP and UFP modes.
o
Low Power:
This module attempts to keep the CCG device in the low power standby mode as often as
possible to minimize power consumption.
o
Host Processor Interface (HPI):
The Host Processor Interface (HPI) is an I
2
C based control interface that
allows an EC to monitor and control the runtime operation of the CCG3 device. CCG3 implements the HPI
using an I
2
C interface, with an interrupt line using a GPIO. In a typical CCG3 notebook application, the EC
may communicate with the CCG3 device to negotiate the power with the connected Type-C device based on
the charge level of the internal battery. CCG3 provides this functionality using commands, responses,
events, and asynchronous messages that are modeled as registers. Detailed documentation on CCG3 HPI
Interface is available. Contact your local Cypress FAE or contact
information.
Solution Management Layer:
This layer consists of the following components:
o
External Hardware Control:
This is a hardware design dependent module that controls the external
hardware blocks such as FETs, regulators, and Type-C switches.
o
Solution specific tasks:
This is an application layer module where any custom tasks required by the user
solution can be implemented.
