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Theory of Operation
2–36
Rev 02; February 8, 2002
2.7.7.2 Back To Back Trigger
Software may want to qualify back to back triggered acquires by polling VBLANK and then issuing a software
trigger to execute an acquire. The problem with this method is, there is only a short period of time between the falling
edge of VBLANK to the falling edge of Vsync, in which you can fire the software trigger to catch the next frame of
video (if software trigger comes at or after Vsync, one field delay is incurred). To facilitate this desired mode of
operation, PCVisionplus allows the user to disable the strobe output (STRBEN bit). With strobe disabled, the Vsync
signal is ignored, allowing a trigger cycle to execute if triggered anywhere within VBLANK (if the trigger is not
received before the rising edge of VBLANK, the next field is missed). This feature gives software a full VBLANK
time to execute the consecutive frame trigger cycles.
2.7.7.3 Stored Trigger
Another feature of the trigger circuit is stored trigger events. By setting the TRIGMD bit, the trigger event inputs can
be latched if a trigger cycle is currently in progress. Normally, PCVisionplus ignores trigger inputs if a trigger cycle
is in progress. By setting TRIGMD, trigger events that occur during a trigger cycle will be latched and execute anoth-
er trigger cycle immediately following the cycle in progress. This mode allows back to back cycles with strobes
enabled, as the new cycle will start immediately prior to Vsync which was shown to incur a field delay.
2.7.7.4 Skip Field Mode
A “skip field” mode is available in all triggered acquire and frame reset cycles. Skip field mode forces the trigger
circuit to skip the first field after the trigger, and acquire starting on the next field. Skip field can be used with cameras
that require a one field delay after a frame reset cycle.
2.7.7.5 Trigger on Frame-Slow Strobe Mode
Slow strobe mode outputs a strobe pulse after the first vertical blank following an external trigger input. Vertical sync
activates the STRBDLY counter which allows the strobe pulse to be positioned a programmable number on lines
after the vertical sync. This allows positioning the strobe pulse with respect to the acquired frame. The strobe pulse is
one line in duration and output polarity is programmable.
In Figure 2–35, the trigger cycle begins on the next vertical blank after the external trigger pulse. At the vertical sync
pulse (Vsync), TRIGEN is cleared and TRIGCYC is set high, indicating the triggered acquire cycle has begun. The
Vsync pulse also starts the strobe delay counter (STRBDLY). The strobe pulse occurs when the STRBDLY count
reaches zero; a programmed number of lines after Vsync. The image memory load begins during the vertical active
region. One or two fields are acquired and loaded into memory, according to the PWG registers.
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