402-00005-00
Theory of Operation
2–24
Rev 02; February 8, 2002
2.7 TIMING CONTROL
Figure 2–24 is a block diagram of the timing control on the PCVisionplus. Timing control is accomplished by the
following circuits:
•
Variable Scan Input
•
Sync Stripper
•
Phase-Locked Loop
•
Programmable Timing Generator (PTG)
•
Programmable Window Generator (PWG)
2.7.1 Variable Scan Inputs
Variable scan refers to any camera format that does not follow any of the standard broadcasting formats (RS170,
CCIR, NTSC, PAL). The standard input formats have pre-defined timing requirements which must be followed;
making interface timing predictable. To interface to non-standard video, the interface circuitry must be capable of
matching the non-standard timing input. The PTG (programmable timing generator), PWG (programmable window
generator), and PLL (phase-locked loop) circuitry are fully programmable allowing acceptance of non-standard vid-
eo formats.
The PCVisionplus supports timing signal inputs: LEN (line enable), FEN (frame enable), CLK (variable scan clock)
from CAM0 or CAM1. Only positive digital signals are supported in variable scan mode. Negative signals and ana-
log timing are not supported. The clock can be input on the CLKIN or FRESET pins of the video connectors.
PCVisionplus requires LEN, FEN, and Pixel Clock all be input in variable scan mode (Vscan mode). Line scan cam-
eras are not supported. In Variable Scan mode the PLL, XTAL and PTG timing sources are disabled and the variable
scan timing is input directly to the PWG for framing the output. Line scan cameras are not supported by the PCVi-
sionplus variable scan inputs. The following describes the required variable scan input timing signals:
CLK, Pixel Clock Input: single-ended TTL, programmable polarity, Frequency 10 KHz to 53 MHz.
LEN, Line Enable Input: single-ended TTL, programmable polarity. Minimum de-asserted or inactive (reset)
pulse duration is one CLK period.
FEN, Frame Enable Input: single-ended TTL, programmable polarity. Minimum de-asserted or inactive (reset)
pulse duration is one CLK period.
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