Contec IPC-BX/M560, Руководство пользователя

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Functions of Components
IPC-BX/M560(PCW)
46
Table 5.10. Register Functions
<2/4>
IIR : Interrupt Identification Register
D7 D6 D5 D4 D3 D2 D1 D0
Interrupt
03FAH
I/O address Contents
LCR : Line Contror Regester
03FBH
1: Interrupt not generated
0: Interrupt generated
0 0 0 0 0
D7 D6 D5 D4 D3 D2 D1 D0
0: 1 stop bit
1: 1.5 stop bit for 5bit length
2 stop bits for 6/7/8bit length
0: Parity disable
1: Parity enable
0: Even parity
1: Odd parity
0: Stick parity disable
1: Stick parity enable
0: Break off
1: Break signal transmit
DLAB (Divisor Latch Access Bit)
Set this bit to 1 to access the divisor latch register.
Set it to 0 to access other registers.
bit2
0
bit1
0
bit0
1
Priority Description
No interrupt is generated
An interrupt is generated at an overrun error,
parity error, framing error, or break interrupt.
An interrupt is generated when the receiver
buffer register goes ready. It is cleared when
the receiver buffer is read.
An interrupt is generated when the transmitter holding
register becomes empty. It is cleared when the IIR is
read or when transmit data is written to the THR.
A modem status interrupt is generated.
(CTS, DSR, RI, CD)
It is cleared when the modem status register is read.
1 1 0
1 0 0
0 1 0
0 0 0
1 (Top)
2
3
4 (Bottom)
D1
0
0
1
1
D0
0
1
0
1
Bit table
5
6
7
8