4. Using the I/O Address Map
ADI16-4(FIT)GY
29
The relationship between a clock cycle and setting data can be expressed as follows:
Sampling clock
250
Clock data =
-1
where the sampling clock is specified in units of
nsec
.
Sampling clock values must satisfy the following expression:
Sampling clock
≥
10000nsec × Number of specified ch 20
µ
sec
(10
µ
sec)
Sampling in accurate cycles cannot be performed if the specified value is shorter than the conversion time for
a specified number of channels.
The control port for setting an internal sampling clock assumes the following state:
Starting
I/O
address
D7
D6
D5
D4
D3
D2
D1
D0
Output
Command
+24
(18h)
0
0
0
0
0
1
0
0
D7
D6
D5
D4
D3
D2
D1
D0
Output
Timer Data 0
+28
(1Ch)
Timer
Data07
Timer
Data06
Timer
Data05
Timer
Data04
Timer
Data03
Timer
Data02
Timer
Data01
Timer
Data00
Timer Data 1
+29
(1Dh)
Timer
Data15
Timer
Data14
Timer
Data13
Timer
Data12
Timer
Data11
Timer
Data10
Timer
Data09
Timer
Data08
Timer Data 2
+30
(1Eh)
Timer
Data23
Timer
Data22
Timer
Data21
Timer
Data20
Timer
Data19
Timer
Data18
Timer
Data17
Timer
Data16
Timer Data 3
+31
(1Fh)
Timer
Data31
Timer
Data30
Timer
Data29
Timer
Data28
Timer
Data27
Timer
Data26
Timer
Data25
Timer
Data24
Figure 4.19. Setting an internal sampling clock
Following are examples in which an internal sampling clock is set :
outp( ADR+24, 0x4 );
outp( ADR+28, ClockData0 );
outp( ADR+29, ClockData1 );
outp( ADR+30, ClockData2 );
outp( ADR+31, ClockData3 );