Contec ADA16-32/2(PCI)F, Руководство пользователя

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6. About Hardware
ADA16-32/2(PCI)F
97
Control Signal Timings
Control Signal Timings for Analog Input
Figures 6.2, 6.3, 6.4, and Table 6.2 show the control signal timings for the analog input function.
t
DEC
External Smapling Clock Input
Conversion start
Figure 6.2. Timing Chart of External Sampling Clock
External Smapling Start Trigger Input
t
HRS
t
SRS
t
HFS
t
SFS
Figure 6.3. Timing Chart of Sampling Start Control Signal
External Smapling Stop Trigger Input
t
HRP
t
SRP
t
HFP
t
SFP
Figure 6.4. Timing Chart of Sampling Stop Control Signal
Table 6.2. Control Signal Timings
Parameter Symbol Time Unit
Delay time from external sampling clock to first A/D start pulse t
DEC
100 nsec
Set up time of sampling start (Rising edge) t
SRS
100 nsec
Hold time of sampling start (Rising edge) t
HRS
100 nsec
Set up time of sampling start (Falling edge) t
SFS
100 nsec
Hold time of sampling start (Falling edge) t
HFS
100 nsec
Set up time of sampling stop (Rising edge) t
SRP
100 nsec
Hold time of sampling stop (Rising edge) t
HRP
100 nsec
Set up time of sampling stop (Falling edge) t
SFP
100 nsec
Hold time of sampling stop (Falling edge) t
HFP
100 nsec
CAUTION
The times listed in Table 6.2 are for standard operating conditions.