Copyright
©
2013
congatec
AG
QMX6m03
53/63
9.11
LPC/GPIO
Table 16 LPC/GPIO Signal Descriptions
Signal
Pin # Description
I/O
PU/PD Comment
LPC_AD0
GPIO0
LPC_AD1
GPIO1
LPC_AD2
GPIO2
LPC_AD3
GPIO3
185
186
187
188
Multiplexed Command, Address and Data (LPC_AD[0..3])
shared with General Purpose Input/Output [0..3]
I/O 3.3V
Shared with GPIO0
Shared with GPIO1
Shared with GPIO2
Shared with GPIO3
LPC_FRAME#
GPIO5
190
LPC frame indicates the start of a new cycle or the termination
of a broken cycle. Shared with General Purpose Input/Output 5
I/O 3.3V
Shared with GPIO5
LPC_LDRQ#
GPIO7
192
LPC DMA request.
General Purpose Input/Output 7
I/O 3.3V
Shared with GPIO7
LPC_CLK
GPIO4
189
LPC clock shared with General Purpose Input/Output 4
I/O 3.3V
The LPC clock output operates at 1/4th of FSB
frequency. By default, the LPC clock is only active
when LPC bus transfers occur. Because of this
behavior, LPC clock must be routed directly to the
bus device; they cannot go through a clock buffer or
other circuit that could delay the signal going to the
end device.
SERIRQ
GPIO6
191
Serialized Interrupt.
General Purpose Input/Output 6
I/O 3.3V PU 10k
3.3V
Shared with GPIO6
Note
The eight LPC pins are configured by default as GPIO’s. Additional eight GPIO pins can be achieved by configuring SDIO pins as GPIO. This
can be programmed in the bootloader and in the kernel.
The conga-QMX6 does not support LPC interface.