Copyright
©
2013
congatec
AG
QMX6m03
50/63
9.7
HDA /I2S /SPDIF
Table 12 HDA/AC’97 Signal Descriptions
Signal
Pin # Description
I/O
PU/PD Comment
HDA_RST#
I2S_RST#
61
HD Audio/AC’97 Codec Reset.
Multiplexed with I2S Codec Reset.
O 3.3V
Connected to GPIO.
HDA_SYNC
I2S_WS
59
Serial Bus Synchronization.
Multiplexed with I2S Word Select from Codec.
O 3.3V
HDA_BITCLK
I2S_CLK
63
HD Audio/AC’97 24 MHz Serial Bit Clock from Codec.
Multiplexed with I2S Serial Data Clock from Codec.
O 3.3V
HDA_SDO
I2S_SDO
67
HD Audio/AC’97 Serial Data Output to Codec.
Multiplexed with I2S Serial Data Output from Codec.
O 3.3V
HDA_SDI
I2S_SDI
65
HD Audio/AC’97 Serial Data Input from Codec.
Multiplexed with I2S Serial Data Input from Codec.
I 3.3V
Note
The conga-QMX6 currently supports only I2S format.
9.8
LVDS
Table 13 LVDS Signal Descriptions
Signal
Pin # Description
I/O
PU/PD Comment
LVDS_PPEN
111
Controls panel power enable.
O 3.3V
LVDS_BLEN
112
Controls panel Backlight enable.
O 3.3V
LVDS_BLT_CTRL
/GP_PWM_OUT0
123
Primary functionality is to control the panel backlight brightness via pulse width
modulation (PWM). When not in use for this primary purpose it can be used as General
Purpose PWM Output.
O 3.3V
LVDS_A0-
e
eDP0_TX0-
99
101
LVDS primary channel differential pair 0.
Display Port primary channel differential pair 0.
O LVDS
LVDS_A1-
e
eDP0_TX1-
103
105
LVDS primary channel differential pair 1.
Display Port primary channel differential pair 1.
O LVDS
LVDS_A2-
e
eDP0_TX2-
107
109
LVDS primary channel differential pair 2.
Display Port primary channel differential pair 2.
O LVDS