COBHAM GRMON3, Руководство пользователя, Страница: 72 / 239

GRMON3-UM
June 2019, Version 3.1.0
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The Example 6.3 has a total of 128 traced bits, divided into twelve signals of various widths. The first signal in
the configuration file maps to the most significant bits of the vector with the traced bits. The created VCD file can
be opened by waveform viewers such as GTKWave or Dinotrace.
Figure 6.1. GTKWave
6.14. Memory controllers
SRAM/SDRAM/PROM/IO memory controllers
Most of the memory controller debug drivers provides switches for timing, wait state control and sizes. They also
probes the memory during GRMON's initialization. In addition they also enables some commands. The mcfg#
sets the reset value
1
of the registers. The info sys shows the timing and amount of detected memory of each type.
Supported cores: MCTRL, SRCTRL, SSRCTRL, FTMCTRL, FTSRCTRL, FTSRCTRL8
mctrl0 European Space Agency LEON2 Memory Controller
AHB: 00000000 - 20000000
AHB: 20000000 - 40000000
AHB: 40000000 - 80000000
APB: 80000000 - 80000100
8-bit prom @ 0x00000000
32-bit sdram: 1 * 64 Mbyte @ 0x40000000
col 9, cas 2, ref 7.8 us
PC133 SDRAM Controller
PC133 SDRAM debug drivers provides switches for timing. It also probes the memory during GRMON's initial-
ization. In addition it also enables the sdcfg1 affects, that sets the reset value
1
of the register. Supported cores:
SDCTRL, FTSDCTRL
DDR memory controller
The DDR memory controller debug drivers provides switches for timing. It also performs the DDR initialization
sequence and probes the memory during GRMON's initialization. It does not enable any commands. The info sys
shows the DDR timing and amount of detected memory. Supported cores: DDRSPA
DDR2 memory controller
The DDR2 memory controller debug driver provides switches for timing. It also performs the DDR2 initialization
sequence and probes the memory during GRMON's initialization. In addition it also enables some commands. The
ddr2cfg# only affect the DDR2SPA, that sets the reset value
1
of the register. The commands ddr2skew and
ddr2delay can be used to adjust the timing. The info sys shows the DDR timing and amount of detected memory
Supported cores: DDR2SPA
ddr2spa0 Cobham Gaisler Single-port DDR2 controller
AHB: 40000000 - 80000000
1
The memory register reset value will be written when GRMON's resets the drivers, for example when run or load is called.