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GRMON3-UM
June 2019, Version 3.1.0
151
www.cobham.com/gaisler
54. l2cache - syntax
NAME
l2cache - L2 cache control
SYNOPSIS
l2cache
subcommand
?
args
?
DESCRIPTION
l2cache lookup
addr
Prints the data and status of a cache line if
addr
generates a cache hit.
l2cache show data ?
way
? ?
count
? ?
start
?
Prints the data of
count
cache line starting at cache line
start
.
l2cache show tag ?
count
? ?
start
?
Prints the tag of
count
cache line starting at cache line
start
.
l2cache enable
Enable the cache.
l2cache disable
l2cache disable flushinvalidate
Disable the cache. If
flushinvalidate
is given, all dirty cache lines are invalidated and written back
to memory as an atomic operation.
l2cache ft ?
boolean
?
Enable or disable the EDAC. If boolean is not set, then the command will show if the EDAC is enabled
or disabled.
l2cache flush
l2cache flush all ?
mode
?
Perform a cache flush to all cache lines using a flush
mode
.
l2cache flush mem
address
?
mode
?
Perform a cache flush to the cache lines with a cache hit for address using a flush
mode
.
l2cache flush direct
address
?
mode
?
Perform a cache flush to the cache lines addressed with address using a flush
mode
.
l2cache invalidate
Invalidate all cache lines
l2cache flushinvalidate
Flush and invalidate all cache lines (copy-back)
l2cache hit
Prints the hit rate statistics.
l2cache wt ?
boolean
?
Enable or disable the write-through. If boolean is not set, then the command will show if write-through
is enabled or disabled.
l2cache hprot ?
boolean
?
Enable or disable the HPROT. If boolean is not set, then the command will show if HPROT is enabled
or disabled.
l2cache smode ?
mode
?
Set the statistics mode. If the
mode
is not set, then the command will show the current statistics mode.
l2cache error
l2cache error inject
l2cache error reset
l2cache error dcb ?
value
?
l2cache error tcb ?
value
?
The l2cache error used to show information about an error in the L2-cache and the information is cleared
with l2cache error reset. I.a. the l2cache error inject can be used to create an error. The l2cache error
dcb and l2cache error tcb can be used to read or write the data/tag check bits.
l2cache mtrr ?
index
? ?
value
?
Show all or a specific memory type range register. If value is present, then the specified register will be set.
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Страница 156: ...GRMON3 UM June 2019 Version 3 1 0 156 www cobham com gaisler SEE ALSO Section 6 13 On chip logic analyzer driver...
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