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GRMON3-UM
June 2019, Version 3.1.0
68
www.cobham.com/gaisler
AHB Master 4
AHB: FF840000 - FF848000
IRQ: 31
Device index: 0
Protection modes: APV and IOMMU
msts: 9, grps: 8, accsz: 128 bits
APV cache lines: 32, line size: 16 bytes
cached area: 0x00000000 - 0x80000000
IOMMU TLB entries: 32, entry size: 16 bytes
translation mask: 0xff000000
Core has multi-bus support
6.9. Multi-processor interrupt controller
The debug driver for IRQMP provides commands for forcing interrupts and reading core status information. The
debug driver also supports ASMP and other extension provided in the IRQ(A)MP core. The IRQMP and IRQAMP
cores are accessed using the command irq, see command description in Appendix B, Command syntax for more
information.
The info sys command displays information on the cores memory map. I.a. if extended interrupts are enabled it
shows the extended interrupt number.
irqmp0 Cobham Gaisler Multi-processor Interrupt Ctrl.
APB: FF904000 - FF908000
EIRQ: 10
6.10. L2-Cache Controller
The debug driver for L2C is accessed using the command l2cache, see command description in Appendix B,
Command syntax for more information. It provides commands for showing status, data and hit-rate. It also provides
commands for enabling/disabling options and flushing or invalidating the cache lines.
If the L2C core has been configured with memory protection, then the l2cache error subcommand can be used
to inject check bit errors and to read out error detection information.
L2-Cache is enabled by default when GRMON starts. This behavior can be disabled by giving the
-nl2c
com-
mand line option which instead disables the cache. L2-Cache can be enabled/disabled later by the user or by soft-
ware in either case. If
-ni
is given, then L2-Cache state is not altered when GRMON starts.
When GRMON is started without
-ni
and
-nl2c
, the L2-Cache controller will be configured with EDAC dis-
abled, LRU replacement policy, no locked ways, copy-back replacement policy and not using
HPROT
to determine
cachability. Pending EDAC error injection is also removed.
When connecting without
-ni
, if the L2-Cache is disabled, the L2-Cache contents will be invalidated to make
sure that any random power-up values will not affect execution. If the L2-Cache was already enabled, it is assumed
that the contents are valid and L2-Cache is flushed to backing memory and then invalidated.
When enabling L2-Cache, the subcommand l2cache disable flushinvalidate can be used to atomically invalidate
and write back dirty lines. The inverse operation is l2cache invalidate followed by l2cache enable. For debugging
the state of L2-Cache itself, it may be more appropriate to use l2cache disable as it does not have any side effects
on cache tags.
The info sys command displays the cache configuration.
l2cache0 Cobham Gaisler L2-Cache Controller
AHB Master 0
AHB: 00000000 - 80000000
AHB: F0000000 - F0400000
AHB: FFE00000 - FFF00000
IRQ: 28
L2C: 4-ways, cachesize: 128 kbytes, mtrr: 16
6.10.1. Switches
-nl2c
Disable L2-Cache on start-up.
Содержание GRMON3
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Страница 156: ...GRMON3 UM June 2019 Version 3 1 0 156 www cobham com gaisler SEE ALSO Section 6 13 On chip logic analyzer driver...
Страница 208: ...GRMON3 UM June 2019 Version 3 1 0 208 www cobham com gaisler SEE ALSO Section 3 5 Tcl integration...