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GRMON3-UM
June 2019, Version 3.1.0
69
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6.11. Statistics Unit
The debug driver for L4STAT provides commands for reading and configuring the counters available in a L4STAT
core. The L4STAT core can be implemented with two APB interfaces. GRMON treats a core with dual interfaces
the same way as it would treat a system with multiple instances of L4STAT cores. If several L4STAT APB
interfaces are found the l4stat command must be followed by an interface index reported by info sys. The info sys
command displays also displays information about the number of counters available and the number of processor
cores supported.
l4stat0 Cobham Gaisler LEON4 Statistics Unit
APB: E4000100 - E4000200
cpus: 2, counters: 4, i/f index: 0
l4stat1 Cobham Gaisler LEON4 Statistics Unit
APB: FFA05000 - FFA05100
cpus: 2, counters: 4, i/f index: 1
The L4STAT core is accessed using the command l4stat, see command description in Appendix B, Command
syntax for more information.
If the core is connected to the DSU it is possible to count several different AHB events. In addition it is possible
to apply filter to the signals connected to the L4STAT (if the DSU supports filter), see command ahb filter
performance in Appendix B, Command syntax.
The l4stat set command is used to set up counting for a specific event. All allowed values for the event parameters
are listed with l4stat events. The number and types of events may vary between systems. Example 6.1 shows
how to set counter zero to count data cache misses on processor one and counter one to count instruction cache
misses on processor zero.
Example 6.1.
grmon3> l4stat 1 events
icmiss - icache miss
itmiss - icache tlb miss
ichold - icache hold
ithold - icache mmu hold
dcmiss - dcache miss
... more events are listed ...
grmon3> l4stat 1 set 0 1 dcmiss
cnt0: Enabling dcache miss on cpu/AHB 1
grmon3> l4stat 1 set 1 0 icmiss
cnt1: Enabling icache miss on cpu/AHB 0
grmon3> l4stat 1 status
CPU DESCRIPTION VALUE
0: cpu1 dcache miss 0000000000
1: cpu0 icache miss 0000000000
2: cpu0 icache miss 0000000000 (disabled)
3: cpu0 icache miss 0000000000 (disabled)
NOTE: Some of the L4STAT events 0x40-0x7F can be counted either per AHB master or independent of master.
The l4stat command will only count events generated by the AHB master specified in the l4stat set command.
The L4STAT debug driver provides two modes that are used to continuously sample L4STAT counters. The driver
will print out the latest read value(s) together with total accumulated amount(s) of events while polling. A poll
operation can either be started directly or be deferred until the run command is issued. In both cases, counters
should first be configured with the type of event to count. When this is done, one of the two following commands
can be issued: l4stat poll
st sp int
The behavior of the first command, l4stat poll, depends on the hold argument. If hold is 0 or not specified, the
specified counter(s) (st - sp) will be enabled and configured to be cleared on read. These counters will then be
polled with an interval of int seconds. After each read, the core will print out the current and accumulated values for
all counters. If the hold argument is 1, GRMON will not initialize the counters. Instead the first specified counter
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Страница 156: ...GRMON3 UM June 2019 Version 3 1 0 156 www cobham com gaisler SEE ALSO Section 6 13 On chip logic analyzer driver...
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