WM8940
Rev 4.4
55
LOOPBACK
Setting the ADC_LOOPBACK or DAC_LOOPBACK register bit enables digital loopback. When the
ADC_LOOPBACK bit is set the output data from the ADC audio interface is fed directly into the DAC
data input. When the DAC_LOOPBACK bit is set the output data from the DAC audio interface is fed
directly to the input of the ADC audio interface.
AUDIO SAMPLE RATES
The WM8940 sample rates for the ADC and the DAC are set using the SR register bits. The cutoffs
for the digital filters and the ALC attack/decay times stated are determined using these values and
assume a 256fs master clock rate.
If a sample rate that is not explicitly supported by the SR register settings is required then the closest
SR value to that sample rate should be chosen, the filter characteristics and the ALC attack, decay
and hold times will scale appropriately.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R7
Additional
control
3:1
SR
000
Approximate sample rate (configures the
coefficients for the internal digital filters):
000=48kHz
001=32kHz
010=24kHz
011=16kHz
100=12kHz
101=8kHz
110-111=reserved
Table 45 Sample Rate Control
MASTER CLOCK AND PHASE LOCKED LOOP (PLL)
The WM8940 has an on-chip phase-locked loop (PLL) circuit that can be used to:
•
Generate master clocks for the WM8940 audio functions from another external clock, e.g.
in telecoms applications.
•
Generate an output clock, on pin CSB/GPIO, for another part of the system (derived from
an existing audio master clock).
Figure 30 shows the PLL and internal clocking arrangement on the WM8940.
The PLL is enabled or disabled by the PLLEN register bit.
Note: In order to minimise current consumption, the PLL is disabled when the VMIDSEL[1:0] bits are set to
00b. VMIDSEL[1:0] must be set to a value other than 00b to enable the PLL.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R1
Power
management 1
5
PLLEN
0
PLL enable
0=PLL off
1=PLL on
Table 46 PLLEN Control Bit
