EGS5 Hardware Interface Description
3.15 Audio Interfaces
75
EGS5_HD_v02.004
Page 69 of 123
2012-02-09
Confidential / Released
3.15.4.2
Slave Mode
In slave mode the PCM interface is controlled by an external bit clock and an external frame
sync signal applied to the BCLKIN and FSIN lines and delivered either by the connected codec
or another source. The bit clock frequency has to be in the range of 256kHz -125ppm to 512kHz
+125ppm.
Data transfer starts at the falling edge of FSIN if the short frame format is selected, and at the
rising edge of FSIN if long frame format is selected. With this edge control the frame sync signal
is independent of the frame sync pulse length.
TXDAI data is shifted out at the rising edge of BCLKIN. RXDAI data (i.e. data transmitted from
the host application to the module's RXDAI line) is sampled at the falling edge of BCLKIN.
The deviation of the external frame rate from the internal frame rate must not exceed ±125ppm.
The internal frame rate of nominal 8kHz is synchronized to the GSM network.
The difference between the internal and the external frame rate is equalized by doubling or
skipping samples. This happens for example every second, if the difference is 125ppm.
The resulting distortion can be neglected in speech signals.
The lines BITCLK and FS remain low in slave mode.
shows the typical slave configuration. The external codec delivers the bit clock and
the frame sync signal. If the codec itself is not able to run in master mode as for example the
MC145483, a third party has to generate the clock and the frame sync signal.
Figure 31:
Slave PCM interface application
