EGS5 Hardware Interface Description
3.13 I
2
C Interface
75
EGS5_HD_v02.004
Page 57 of 123
2012-02-09
Confidential / Released
3.13
I
2
C Interface
I
2
C is a serial, 8-bit oriented data transfer bus for bit rates up to 400 kbps in Fast mode. It con-
sists of two lines, the serial data line I2CDAT and the serial clock line I2CCLK.
The EGS5 module acts as a single master device, e.g. the clock I2CCLK is driven by module.
I2CDAT is a bi-directional line. Each device connected to the bus is software addressable by a
unique 7-bit address, and simple master/slave relationships exist at all times. The module op-
erates as master-transmitter or as master-receiver. The customer application transmits or re-
ceives data only on request of the module.
To configure and activate the I
2
C bus use the AT^SSPI command. If the I
2
C bus is active the
two lines I2CCLK and I2DAT are locked for use as SPI lines. Vice versa, the activation of the
SPI locks both lines for I
2
C. Detailed information on the AT^SSPI command as well explana-
tions on the protocol and syntax required for data transmission can be found in
The I
2
C interface can be powered from an external supply or via the VEXT line of EGS5. If con-
nected to the VEXT line the I
2
C interface will be properly shut down when the module enters
the Power-down mode. If you prefer to connect the I
2
C interface to an external power supply,
take care that VCC of the application is in the range of VEXT and that the interface is shut down
when the PWR_IND signal goes high. See figures below as well as
and
In the application I2CDAT and I2CCLK lines need to be connected to a positive supply voltage
via a pull-up resistor. For electrical characteristics please refer to
Figure 19:
I
2
C interface connected to VCC of application
Figure 20:
I
2
C interface connected to VEXT line of
EGS5
Note: Good care should be taken when creating the PCB layout of the host application: The
traces of I2CCLK and I2CDAT should be equal in length and as short as possible.
