EGS5 Hardware Interface Description
3.15 Audio Interfaces
75
EGS5_HD_v02.004
Page 67 of 123
2012-02-09
Confidential / Released
3.15.4.1
Master Mode
To clock input and output PCM samples the PCM interface delivers a bit clock (BITCLK) which
is synchronous to the GSM system clock. The frequency of the bit clock is 256kHz or 512kHz.
Any edge of this clock deviates less than ±100ns (Jitter) from an ideal 256kHz clock respec-
tively deviates less than ±320ns from an ideal 512kHz clock.
The frame sync signal (FS) has a frequency of 8kHz and is high for one BITCLK period before
the data transmission starts if short frame is configured. If long frame is selected the frame sync
signal (FS) is high during the whole transfer of the 16 data bits. Each frame has a duration of
125µs and contains 32 respective 64 clock cycles.
Figure 28:
Master PCM interface Application
Table 18:
Overview of DAI signal functions
Signal name
Function for PCM Interface
Input/Output
DAI0
TXDAI
Master/Slave
O
DAI1
RXDAI
Master/Slave
I
DAI2
FS (Frame sync)
Master
O
DAI3
BITCLK
Master
O
DAI4
FSIN
Slave
I
DAI5
BCLKIN
Slave
I
DAI6
nc
I
