Campbell CR23X, Руководство оператора

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SECTION 9. INPUT/OUTPUT INSTRUCTIONS
9-3
•
Control Ports
The switch closure is connected
between channels C5..C8 and the 5 V
terminal. When the switch is open, the
control port is pulled to ground through
an internal 100 kOhm resistor. When
the switch is closed, the control port is
at 5 V. The count is incremented when
the switch closes.
Maximum Frequency: 40 Hz
Minimum Switch Closed Time: 6 ms
Minimum Switch Open Time: 6 ms
High Precision Measurements
Maximum Program Execution
Interval: < 4.0 s
Minimum Frequency: > 0.25 Hz
Pulse Channel Details: Counters, Resets,
and Accumulators
Each of the four pulse channels (P1..P4) have
an 8 bit counter. The 8 bit counters each have
a limit of 255 counts per reset. The 8 bit
counter reset will be every 0.01 s (100 Hz),
0.02 s (50 Hz), 0.05 s (20 Hz), or 0.1 s (10 Hz).
Table 9-2 shows the maximum input frequency
allowed at each reset interval.
TABLE 9-2. 8 Bit Counter Reset Interval and
Maximum Input Frequency
Counter Counter Maximum
Reset Reset Input
Interval (s) Frequency (Hz) Frequency (kHz)
0.01 100 25.50
0.02 50 12.75
0.05 20 5.10
0.10 10 2.55
By default, the CR23X will determine which
reset interval to use based on the datalogger’s
programmed execution interval. The CR23X
sets the reset interval to the largest reset
interval (0.01, 0.02, 0.05, or 0.10) that evenly
divides into the execution interval. For
clarification, Table 9-3 shows some examples
of execution intervals and corresponding
counter reset intervals.
As counter reset frequency increases,
quiescent current drain of the CR23X increases.
If power consumption is less of a concern,
parameter 3 of the Pulse Counter (P3)
instruction can be indexed (e.g. 03: 0--).
Indexing the 3
rd
parameter in any P3 Pulse
Counter instruction will invoke a 100 Hz reset
frequency on all pulse channels (P1..P4).
Higher input frequencies can be counted by
combining two counters on one input channel.
The resulting 16 bit counter allows input
frequencies up to 400 kHz. This option is valid
only on P1 or P3; the subsequent channel, P2
or P4, becomes inactive. So, maximum
number of Reps (parameter 1 in Instruction 3) is
4 when using 8 bit counters, and 2 when using
16 bit counters.
CR23X power usage increases as maximum
input frequency increases.
At the reset interval, the processor transfers the
values from the counters into 16 bit
accumulators. The counters are then hardware
reset to zero. The accumulators accumulate up
to 65, 535 counts. Counts accumulate in the
accumulators until the program table containing
Pulse Count Instruction 3 is executed.
The
execution interval of the table must be short
enough that the accumulator does not
overflow.
At the beginning of the execution of
the program table (or before each pass through
a P87 loop with a delay), totals in the
accumulators are transferred to a temporary
RAM buffer. The accumulator is then zeroed.
When the execution reaches Pulse Count
Instruction 3, the value in the RAM buffer is
multiplied by the multiplier, added to the offset,
then placed into the designated input location.