6.5.4 SCPI Status Model
All SCPI instruments implement status registers in the same way. The status
system records various instrument conditions in three register groups:
The Status Byte register
The Standard Event register and
The Questionable Data register.
The status byte register records high level summary information reported in the
other register groups.
The diagram on the next page illustrates the SCPI status system.
Event Registers:
The standard and the questionable data registers have event registers. An
event register is a read-only register that reports defined conditions within the instru-
ment. Bits in the event registers are latched. Once an event bit is set, subsequent
state changes are ignored. Bits in an event register are automatically cleared by a
query of that register (such as *ESR? or STAT: QUES: EVEN?) or by sending the
*CLS (clear status) command. A reset (*RST) or device clear will not clear bits in
event registers. Querying an event register returns a decimal value, which corre-
sponds, to the binary weighted sum of all bits set in that register.
Enable Registers:
An enable register defines which bits in the corresponding event register are
logically Ored together to form a single summary bit. Enable registers are both
readable and writable. The *CLS (clear status) command does not clear enable
registers but it does clear the bits in the event registers. The STATus:PRESet com-
mand will clear the questionable data enable register. Querying an enable register
will not clear it. To enable bits in an enable register, you must write a decimal value,
which corresponds, to the binary weighted sum of bits you wish to enable in a
register.
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