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SPCA717A
© Sunplus Technology Co., Ltd.
Proprietary & Confidential
241 NOV. 11, 2002
Preliminary Version: 0.1
6.9. Pixel Input Ranges And Colorspace Conversion
6.10. YC inputs (4:2:2 YCRCB)
Y has a nominal range of 16-235; Cb and Cr have a nominal
range of 16-240, with 128 equal to zero. Y values of 0-15 and
236-255 are interpreted as 16 and 235. CrCb values of 1-15 and
241-254, are interpreted as 16 and 240.
6.11. DAC coding
White is represented by a 9-bit DAC code of 400. For PAL-B, D,
G, H, I, Nc the standard blanking level is represented by a DAC
code of 126. For NTSC, the standard blanking level is
represented by a DAC code of 120.
6.12. Outputs
All digital-to-analog converters are designed to drive standard
video levels into an equivalent 37.5
Ω
load. Either tone composite
video outputs or Y outputs are available (selectable by
the LUMA pin). If the SLEEP pin is high, the DAC are essentially
turned off and only the leakage current is present.
6.12.1. Composite and luminance (CVBS/Y) analog
output
When LUMA is a logical zero, digital composite video information
drives the 9-bit D/A converter that generates the CVBS output.
When LUMA is a logical one, digital luminance information drives
the DAC that generates the analog Y video output.
Содержание PV420S
Страница 1: ...SERVICE MANUAL PV420S WWW BBK RU ...
Страница 72: ... 69 CXD3068Q Block Diagram ...
Страница 73: ... 70 CXD3068Q Pin Configuration ...
Страница 122: ... 119 CXD3068Q Timing Chart 1 3 ...
Страница 123: ... 120 CXD3068Q Timing Chart 1 4 ...
Страница 124: ... 121 CXD3068Q Timing Chart 1 5 ...
Страница 127: ... 124 CXD3068Q Timing Chart 1 16 CAV W mode EPWM 1 LPWR 0 Timing Chart 1 17 CAV W mode EPWM LPWR 1 ...
Страница 129: ... 126 CXD3068Q Timing Chart 2 1 ...
Страница 130: ... 127 CXD3068Q Block Diagram 2 2 ...
Страница 131: ... 128 CXD3068Q Timing Chart 2 3 ...
Страница 134: ... 131 CXD3068Q Timing Chart 2 6 ...
Страница 137: ... 134 CXD3068Q Fig 3 1 Disc Stop to Regular Playback in CLV W Mode CLV W Mode Fig 3 2 CLV W Mode Flow Chart ...
Страница 138: ... 135 CXD3068Q VCO C Mode Fig 3 3 Access Flow Chart Using VCO Control ...
Страница 140: ... 137 CXD3068Q Block Diagram 4 1 ...
Страница 143: ... 140 CXD3068Q Timing Chart 4 4 ...
Страница 147: ... 144 CXD3068Q Fig 4 6 a Auto Focus Flow Chart Fig 4 6 b Auto Focus Timing Chart ...
Страница 148: ... 145 CXD3068Q Fig 4 7 a 1 Track Jump Flow Chart Fig 4 7 b 1 Track Jump Timing Chart ...
Страница 149: ... 146 CXD3068Q Fig 4 8 a 10 Track Jump Flow Chart Fig 4 8 b 10 Track Jump Timing Chart ...
Страница 150: ... 147 CXD3068Q Fig 4 9 a 2N Track Jump Flow Chart Fig 4 9 b 2N Track Jump Timing Chart ...
Страница 151: ... 148 CXD3068Q Fig 4 10 a Fine Search Flow Chart Fig 4 10 b Fine Search Timing Chart ...
Страница 152: ... 149 CXD3068Q Fig 4 11 a M Track Move Flow Chart Fig 4 11 b M Track Move Timing Chart ...
Страница 157: ... 154 CXD3068Q Fig 4 15 CD TEXT Data Timing Chart ...
Страница 162: ... 159 CXD3068Q Fig 5 3a Fig 5 3b ...
Страница 176: ... 173 CXD3068Q Fig 5 26a Servo HighBooster Characteristics FCS TRK MCK 128Fs HBST1 0 HBST1 1 HBST0 0 HBST1 1 HBST0 1 ...
Страница 177: ... 174 CXD3068Q Fig 5 26b Servo LowBooster1 Characteristics FCS TRK MCK 128Fs LB1S1 0 LB1S1 1 LB1S0 0 LB1S1 1 LB1S0 1 ...
Страница 178: ... 175 CXD3068Q Fig 5 26c Servo LowBooster2 Characteristics FCS TRK MCK 128Fs LB2S1 0 LB2S1 1 LB2S0 0 LB2S1 1 LB2S0 1 ...
Страница 196: ... 193 CXD3068Q Description of Data Readout ...
Страница 200: ... 197 CXD3068Q ...
Страница 201: ... 198 CXD3068Q ...
Страница 202: ... 199 CXD3068Q ...
Страница 203: ... 200 CXD3068Q SLD Servo fs 345Hz Note Set the MSB bit of the K02 and K04 coefficients to 0 HPTZC Auto Gain fs 88 2kHz ...
Страница 207: ... 204 CXD3068Q Package Outline Unit mm ...
Страница 208: ...This data sheet has been made from recycled paper to help protect the environment 205 ...